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公开(公告)号：US11656790B2
公开(公告)日：2023-05-23
申请号：US17654052
申请日：2022-03-08
Applicant: SK hynix Inc.
Inventor： Seung Gu Ji , Hyung Min Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0652 , G06F3/0679
Abstract: Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.
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公开(公告)号：US11467910B2
公开(公告)日：2022-10-11
申请号：US17034444
申请日：2020-09-28
Applicant: SK hynix Inc.
Inventor： Hyung Min Lee , Yong Il Jung
Abstract: A memory system includes a memory device; and a controller configured to transmit a target address to the memory device for performing an access operation, receive from the memory device a reference address at which the access operation has been performed, and selectively re-perform the access operation based on the reference address. The controller re-performs the access operation when the reference address is different from the target address.
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公开(公告)号：US10566067B2
公开(公告)日：2020-02-18
申请号：US16191793
申请日：2018-11-15
Applicant: SK hynix Inc.
Inventor： Hyung Min Lee
Abstract: The operation of a semiconductor memory device may be controlled by a method of operating a memory controller. The operating method may include transmitting a first read command to the semiconductor memory device, and determining whether to generate a discharge command based on the type of command waiting to be transmitted after the first read command.
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公开(公告)号：US10186324B2
公开(公告)日：2019-01-22
申请号：US15785567
申请日：2017-10-17
Applicant: SK hynix Inc.
Inventor： Hyung Min Lee
Abstract: A method for operating a memory system includes determining at least one erased memory cell among a plurality of erased memory cells as an unstable memory cell based on read data read from the at least one erased memory cell; determining the unstable memory cell as an unwritable memory cell based on write data to be written in the unstable memory cell; and prohibiting the plurality of erased memory cells from being used, depending on the number of erased memory cells as the unwritable memory cell among the plurality of erased memory cells.
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公开(公告)号：US09570189B1
公开(公告)日：2017-02-14
申请号：US15097793
申请日：2016-04-13
Applicant: SK hynix Inc.
Inventor： Jae Yoon Lee , Hyung Min Lee , Myeong Woon Jeon
CPC classification number: G11C16/3404 , G06F11/1068 , G11C16/0483 , G11C16/28 , G11C16/3418 , G11C16/3422
Abstract: A data storage device includes a nonvolatile memory device including a target memory cell and one or more adjustment memory cells sharing bit lines with the target memory cell, one or more of the adjustment memory cell are adjacent memory cells adjacent to the target memory cells, and suitable for reading out data therefrom or storing data therein; and a controller suitable for adjusting threshold voltages of the adjustment memory cells based on threshold voltages it of the target memory cell and the adjacent memory cells.
Abstract translation: 数据存储装置包括非易失性存储装置，包括目标存储单元和与目标存储单元共用位线的一个或多个调整存储单元，调整存储单元中的一个或多个与所述目标存储单元相邻的存储单元相邻，以及 适用于从中读出数据或在其中存储数据; 以及适合于基于目标存储器单元和相邻存储器单元的阈值电压来调整调整存储器单元的阈值电压的控制器。
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Patent Agency Ranking
公开(公告)号：US20140063944A1
公开(公告)日：2014-03-06
申请号：US13726924
申请日：2012-12-26
Applicant: SK HYNIX INC.
Inventor： Hyung Min Lee
IPC: G11C29/04
CPC classification number: G11C29/04 , G11C16/3404 , G11C29/42 , G11C29/52 , G11C2029/0409
Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell block configured to have memory cell groups, a peripheral circuit configured to read data by supplying a read voltage to memory cells in the memory cell groups, a fail detection circuit configured to perform a pass/fail check operation of memory cell groups according to the data read by the peripheral circuit and a control circuit configured to control the peripheral circuit and the fail detection circuit to perform again the read operation about the memory cell groups using a compensation read voltage different from the read voltage in the event that it is determined that one or more memory cell group is failed according to the pass/fail check operation.
Abstract translation: 公开了一种半导体存储器件及其操作方法。 半导体存储器件包括配置为具有存储单元组的存储单元块，被配置为通过向存储单元组中的存储单元提供读取电压来读取数据的外围电路，配置为执行通过/失败检查操作的故障检测电路 的存储单元组;以及控制电路，被配置为控制外围电路和故障检测电路，以使用与读取电压不同的补偿读取电压再次执行关于存储单元组的读取操作 根据通过/失败检查操作确定一个或多个存储单元组发生故障的事件。
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公开(公告)号：US11307794B2
公开(公告)日：2022-04-19
申请号：US17095175
申请日：2020-11-11
Applicant: SK hynix Inc.
Inventor： Seung Gu Ji , Hyung Min Lee
IPC: G06F3/06
Abstract: Memory systems, memory controllers, and operation methods of the memory systems are disclosed. In one example aspect, the memory system may suspend a target operation, such as a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. In this way, the memory system may reduce a delay associated with the suspension of program operations and erasure operations.
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公开(公告)号：US10817377B2
公开(公告)日：2020-10-27
申请号：US16026550
申请日：2018-07-03
Applicant: SK hynix Inc.
Inventor： Hyung Min Lee , Yong Il Jung
Abstract: A memory system includes a memory device; and a controller configured to transmit a target address to the memory device for performing an access operation, receive from the memory device a reference address at which the access operation has been performed, and selectively re-perform the access operation based on the reference address. The controller re-performs the access operation when the reference address is different from the target address.
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公开(公告)号：US08737128B2
公开(公告)日：2014-05-27
申请号：US13726924
申请日：2012-12-26
Applicant: SK hynix Inc.
Inventor： Hyung Min Lee
IPC: G11C16/06
CPC classification number: G11C29/04 , G11C16/3404 , G11C29/42 , G11C29/52 , G11C2029/0409
Abstract: A semiconductor memory device and a method of operating the same are disclosed. The semiconductor memory device includes a memory cell block configured to have memory cell groups, a peripheral circuit configured to read data by supplying a read voltage to memory cells in the memory cell groups, a fail detection circuit configured to perform a pass/fail check operation of memory cell groups according to the data read by the peripheral circuit and a control circuit configured to control the peripheral circuit and the fail detection circuit to perform again the read operation about the memory cell groups using a compensation read voltage different from the read voltage in the event that it is determined that one or more memory cell group is failed according to the pass/fail check operation.
Abstract translation: 公开了一种半导体存储器件及其操作方法。 半导体存储器件包括配置为具有存储单元组的存储单元块，被配置为通过向存储单元组中的存储单元提供读取电压来读取数据的外围电路，配置为执行通过/不通过检查操作的故障检测电路 的存储单元组;以及控制电路，被配置为控制外围电路和故障检测电路，以使用与读取电压不同的补偿读取电压再次执行关于存储单元组的读取操作 根据通过/失败检查操作确定一个或多个存储单元组发生故障的事件。
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公开(公告)号：US12197770B2
公开(公告)日：2025-01-14
申请号：US18170501
申请日：2023-02-16
Applicant: SK hynix Inc.
Inventor： Seung Gu Ji , Hyung Min Lee
IPC: G06F3/06
Abstract: Embodiments of the disclosed technology relate to a memory system, a memory controller, and an operation method of the memory system. Based on embodiments of the disclosed technology, the memory system may suspend a target operation, which is a program operation or an erase operation, based on whether or not to execute a first operation of resetting a reference read bias when a failure occurs in a read operation executed after the target operation is suspended, and a number of times the target operation is suspended. Accordingly, the memory system is capable of preventing a problem in that the end time of a program operation or an erase operation is excessively delayed, and controlling the number of times a program operation or an erase operation is suspended.
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