公开(公告)号：US09990312B2

公开(公告)日：2018-06-05

申请号：US15257389

申请日：2016-09-06

Applicant: SK hynix Inc.

Inventor： Sung-Eun Lee ,  Jung-Hyun Kwon ,  Jing-Zhe Xu ,  Yong-Ju Kim

IPC: G06F3/00 ,  G06F13/16 ,  G11C29/00 ,  G06F13/40

CPC classification number: G06F13/161 ,  G06F13/1684 ,  G06F13/4027 ,  G06F13/404 ,  G11C29/76 ,  G11C29/88

Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

公开(公告)号：US10474376B2

公开(公告)日：2019-11-12

申请号：US15598418

申请日：2017-05-18

Applicant: SK hynix Inc.

Inventor： Jing-Zhe Xu ,  Jung-Hyun Kwon ,  Sung-Eun Lee ,  Jae-Sun Lee ,  Sang-Gu Jo

IPC: G06F12/12 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: An operating method of a memory controller may include determining a physical page to be accessed in a plurality of memory devices by mapping a logical address to a physical address; and determining a distribution pattern in which data of the physical page are distributed to the plurality of memory devices using the logical address.

公开(公告)号：US09627095B1

公开(公告)日：2017-04-18

申请号：US15230122

申请日：2016-08-05

Applicant: SK hynix Inc.

Inventor： Jing-Zhe Xu ,  Yong-Ju Kim ,  Jung-Hyun Kwon ,  Sung-Eun Lee ,  Jae-Sun Lee

IPC: G11C29/00 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C17/16

CPC classification number: G11C29/76 ,  G06F12/0246 ,  G11C5/04 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C17/16 ,  G11C29/72 ,  G11C29/78 ,  G11C29/781 ,  G11C29/808 ,  G11C29/814 ,  G11C29/832 ,  G11C29/84 ,  G11C29/886

Abstract: A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.