公开(公告)号：US12224747B2

公开(公告)日：2025-02-11

申请号：US18343537

申请日：2023-06-28

Applicant: SK hynix Inc.

Inventor： Chae Sung Lim ,  Jung Taek You ,  Saeng Hwan Kim ,  Sang Sic Yoon ,  Hong Joo Song

IPC: H03K19/00 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

公开(公告)号：US09287010B1

公开(公告)日：2016-03-15

申请号：US14607699

申请日：2015-01-28

Applicant: SK hynix Inc.

Inventor： Jung Taek You ,  Byung Kuk Yoon

IPC: G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C17/16

CPC classification number: G11C29/78 ,  G11C29/44 ,  G11C29/56008

Abstract: A repair system for a semiconductor apparatus includes a tester configured to generate memory repair data including a die identification information and repair addresses, and a command to perform a repair process; and a semiconductor apparatus including a plurality of dies configured to receive the memory repair data, wherein one of the dies corresponding to the die identification information performs a repair operation according to the repair addresses and the command.

Abstract translation: 一种用于半导体装置的修复系统包括：测试器，被配置为产生包括管芯识别信息和修复地址的存储器修复数据，以及执行修复处理的命令; 以及包括多个管芯的半导体装置，其被配置为接收所述存储器修复数据，其中与所述管芯识别信息相对应的管芯中的一个根据所述修复地址和所述命令执行修复操作。

公开(公告)号：US12198784B2

公开(公告)日：2025-01-14

申请号：US18116001

申请日：2023-03-01

Applicant: SK hynix Inc.

Inventor： Jung Taek You ,  Sang Sic Yoon ,  Kyu Dong Hwang ,  Chae Sung Lim ,  Saeng Hwan Kim ,  Hong Joo Song

IPC: G11C7/22 ,  G06F13/16 ,  G06F13/40 ,  G11C7/10

Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

公开(公告)号：US09583214B2

公开(公告)日：2017-02-28

申请号：US14018046

申请日：2013-09-04

Applicant: SK hynix Inc.

Inventor： Jung Taek You ,  Min Joo Yoo

IPC: G01R31/11 ,  G11C29/02 ,  G11C29/56 ,  G11C29/50

CPC classification number: G11C29/022 ,  G11C29/025 ,  G11C29/56 ,  G11C2029/5006 ,  G11C2029/5602

Abstract: A semiconductor circuit includes a test control unit configured to generate a driving activation signal and a sensing activation signal in response to a command and an address; a pad; a driver configured to drive the pad to a predetermined level in response to activation of the driving activation signal; and a sensing unit configured to compare a voltage level of the pad with a reference voltage in response to activation of the sensing activation signal, and output a sensing signal.

Abstract translation: 半导体电路包括：测试控制单元，被配置为响应于命令和地址产生驱动启动信号和感测激活信号; 垫子 驱动器，配置为响应于所述驱动激活信号的激活而将所述焊盘驱动到预定水平; 以及感测单元，被配置为响应于所述感测激活信号的激活而将所述焊盘的电压电平与参考电压进行比较，并且输出感测信号。

公开(公告)号：US09672890B2

公开(公告)日：2017-06-06

申请号：US14802178

申请日：2015-07-17

Applicant: SK hynix Inc.

Inventor： Jung Taek You

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408 ,  G11C7/08 ,  G11C11/4091 ,  G11C29/50

CPC classification number: G11C11/406 ,  G11C7/08 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4091 ,  G11C29/50016

Abstract: A semiconductor memory apparatus includes a plurality of cell arrays; and a use information storage block configured to determine whether a data write operation has already been performed for the plurality of cell arrays, and generate a plurality of control signals, wherein the semiconductor memory apparatus is configured to control a refresh operation for the plurality of cell arrays according to the plurality of control signals.

公开(公告)号：US09401218B2

公开(公告)日：2016-07-26

申请号：US14573707

申请日：2014-12-17

Applicant: SK hynix Inc.

Inventor： Jung Taek You

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/20 ,  G11C17/16

Abstract: A fuse circuit includes an E-fuse array including a plurality of E-fuse elements configured to store fuse data; a latch block including a plurality of latch groups configured to latch the fuse data read from the E-fuse array; and a control block configured to output latch reset signals corresponding to the plurality of latch groups in response to an apparatus reset signal and a clock signal, wherein the control block sequentially enables the latch reset signals.

Abstract translation: 熔丝电路包括一个E熔丝阵列，它包括配置成存储熔丝数据的多个E熔丝元件; 锁存块，包括多个闩锁组，其被配置为锁存从所述E熔丝阵列读取的所述熔丝数据; 以及控制块，其被配置为响应于设备复位信号和时钟信号而输出与所述多个锁存器组相对应的锁存复位信号，其中所述控制块顺序启用所述锁存复位信号。