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21 条记录 (耗时 0.015 秒)

    Semiconductor device capable of preventing reset of counting circuit
    1.
    发明授权
    Semiconductor device capable of preventing reset of counting circuit 有权

    公开(公告)号：US10523212B2

    公开(公告)日：2019-12-31

    申请号：US16103730

    申请日：2018-08-14

    申请人： SK hynix Inc.

    发明人： Kyu Dong Hwang

    IPC分类号： H03K21/10 ,  H03K21/38 ,  H03K21/02

    摘要： A semiconductor device may include an input control circuit, a counting circuit, an output control circuit, and a counting operation control circuit. The input control circuit may output a counting input signal based on an input signal and a counting over signal. The counting circuit may generate a preliminary counting code based on the counting input signal. The output control circuit may generate a counting code based on the preliminary counting code. The counting operation control circuit may generate the counting over signal based on a part of the counting code.

    Buffering circuit, and semiconductor apparatus and system including buffering circuit
    3.
    发明授权
    Buffering circuit, and semiconductor apparatus and system including buffering circuit 有权

    公开(公告)号：US10720199B2

    公开(公告)日：2020-07-21

    申请号：US16218181

    申请日：2018-12-12

    申请人： SK hynix Inc.

    发明人： Kyu Dong Hwang ,  Dae Han Kwon

    IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C13/00

    摘要： A buffering circuit includes a first signal input/output unit that generates an output bar signal in response to an input signal, a second signal input/output unit that generates an output signal in response to an input bar signal, and a connection unit that electrically connects and disconnects an output node of the first signal input/output unit and a current sink node of the second signal input/output unit to/from each other in response to a control signal, and electrically connects and disconnects a current sink node of the first signal input/output unit and an output node of the second signal input/output unit to/from each other in response to the control signal.

    Clock distribution circuit and semiconductor device including the clock distribution circuit
    6.
    发明授权
    Clock distribution circuit and semiconductor device including the clock distribution circuit 有权

    公开(公告)号：US11385674B2

    公开(公告)日：2022-07-12

    申请号：US16890717

    申请日：2020-06-02

    申请人： SK hynix Inc.

    发明人： Soo Young Jang ,  Dae Han Kwon ,  Geun Il Lee ,  Kyu Dong Hwang

    IPC分类号： G06F1/10 ,  H03K19/0185 ,  H03L7/189

    摘要： A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

    Transmitter for transmitting a duobinary signal
    7.
    发明授权
    Transmitter for transmitting a duobinary signal 有权

    公开(公告)号：US11374570B1

    公开(公告)日：2022-06-28

    申请号：US17395288

    申请日：2021-08-05

    申请人： SK hynix Inc. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

    发明人： Dongsuk Kang ,  Jaewoo Park ,  Jung-Hoon Chun ,  Kyu Dong Hwang ,  Dae Han Kwon

    IPC分类号： H03K19/00 ,  H03K19/017 ,  H03K19/09 ,  H03K19/17772

    摘要： A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.

    Semiconductor device and system
    8.
    发明授权
    Semiconductor device and system 有权

    公开(公告)号：US10482942B2

    公开(公告)日：2019-11-19

    申请号：US15947382

    申请日：2018-04-06

    申请人： SK hynix Inc.

    发明人： Sang Kwon Lee ,  Kwang Soon Kim ,  Young Hoon Kim ,  Young Jun Yoon ,  Kyu Dong Hwang

    IPC分类号： G11C7/00 ,  G11C11/34 ,  G11C7/22 ,  G11C7/10

    摘要： A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference voltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US11855596B2

    公开(公告)日：2023-12-26

    申请号：US17175504

    申请日：2021-02-12

    申请人： SK hynix Inc.

    发明人： Kyu Dong Hwang

    IPC分类号： H03F3/45

    CPC分类号： H03F3/45179

    摘要： An amplifier circuit includes a first input unit, a second input unit, a first current supply unit, and a second current supply unit. The first input unit changes a voltage level of a first output node based on a first input signal. The second input unit changes a voltage level of a second output node based on a second input signal. The first current supply unit supplies a first current to the first output node based on a voltage level of the first output node and boosts the voltage level of the first output node for a predetermined time when the voltage level of the first output node is changed. The second current supply unit supplies a second current to the second output node based on the voltage level of the first output node.

    Clock compensation circuit
    10.
    发明授权
    Clock compensation circuit 有权

    公开(公告)号：US11409324B2

    公开(公告)日：2022-08-09

    申请号：US17372035

    申请日：2021-07-09

    申请人： SK hynix Inc.

    发明人： Gi Moon Hong ,  Kyu Dong Hwang

    IPC分类号： G06F1/10 ,  H03K5/26 ,  G06F1/06 ,  H02M3/07 ,  H03K5/00 ,  H03K21/02

    摘要： A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.