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Patent Agency Ranking
公开(公告)号：US10333542B2
公开(公告)日：2019-06-25
申请号：US15996082
申请日：2018-06-01
Applicant: SK hynix Inc.
Inventor： Keunjin Chang
Abstract: According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a plurality of paths corresponding to bit currents, respectively. The digital-to-analog converter may include a switching circuit configured to include a plurality of weighted elements respectively coupled to the paths. The digital-to-analog converter may include a reference voltage setting circuit coupled to the weighted elements and the paths, and configured to minimize a variation of threshold voltages of the weighted elements.
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公开(公告)号：US10135457B2
公开(公告)日：2018-11-20
申请号：US15821225
申请日：2017-11-22
Applicant: SK hynix Inc.
Inventor： Keunjin Chang
Abstract: A successive approximation register analog-digital converter including a split-capacitor based digital-analog converter includes a comparator, a split-capacitor based digital-analog converter including a positive capacitor array and a negative capacitor array, and a successive approximation register logic. The positive capacitor array and the negative capacitor array each includes a positive capacitor array of a first stage and a negative capacitor array of a first stage that generate input signals of the comparator corresponding to upper bits including an MSB, respectively, a positive capacitor array of a second stage and a negative capacitor array of a second stage that generate input signals corresponding to intermediate bits, and a positive capacitor array of a third stage and a negative capacitor array of a third stage that generate input signals corresponding to lower bits of an LSB and a next to bit of the LSB.
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公开(公告)号：US10084465B2
公开(公告)日：2018-09-25
申请号：US15651694
申请日：2017-07-17
Applicant: SK hynix Inc.
Inventor： Keunjin Chang , Joo Won Oh , Donghoon Sung
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/1205 , H03M1/144 , H03M1/204 , H03M1/361 , H03M1/745
Abstract: An analog-to-digital converter ADC may be provided. The ADC may include a current driving circuit. The current driving circuit may include an additive current driving circuit and a subtractive current driving circuit configured for adjusting a voltage level of a node. The ADC may include a comparison circuit including a plurality of comparators. Each of the plurality of comparators may be configured to compare a voltage level of the node with a reference voltage.
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公开(公告)号：US10324573B2
公开(公告)日：2019-06-18
申请号：US15656584
申请日：2017-07-21
Applicant: SK hynix Inc.
Inventor： Keunjin Chang
Abstract: A sensing device may include an integrator configured to sense electrical characteristics of first and second nodes to generate an output voltage. A sensing device may include a switching portion configured to include a plurality of switches, wherein the plurality of switches operate to connect at least one of the plurality of switches to the first node and to connect the remaining switches of the plurality of switches to the second node during each of a plurality of successive switching cycles.
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公开(公告)号：US20190131996A1
公开(公告)日：2019-05-02
申请号：US15996082
申请日：2018-06-01
Applicant: SK hynix Inc.
Inventor： Keunjin Chang
CPC classification number: H03M1/183 , H03M1/00 , H03M1/0612 , H03M1/0646 , H03M1/1057 , H03M1/447 , H03M1/66 , H03M1/785 , H03M1/80
Abstract: According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a plurality of paths corresponding to bit currents, respectively. The digital-to-analog converter may include a switching circuit configured to include a plurality of weighted elements respectively coupled to the paths. The digital-to-analog converter may include a reference voltage setting circuit coupled to the weighted elements and the paths, and configured to minimize a variation of threshold voltages of the weighted elements.
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