公开(公告)号：US20210217472A1

公开(公告)日：2021-07-15

申请号：US17214592

申请日：2021-03-26

Applicant: SK hynix Inc.

Inventor： Ki Won LEE ,  Seok Man HONG ,  Tae Hoon KIM ,  Hyung Dong LEE

IPC: G11C13/00

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

公开(公告)号：US20190333555A1

公开(公告)日：2019-10-31

申请号：US16203351

申请日：2018-11-28

Applicant: SK hynix Inc.

Inventor： Hyuck Sang YIM ,  Ki Won LEE ,  Seoung Ju CHUNG

IPC: G11C8/06 ,  G11C8/20 ,  G11C8/18 ,  G11C8/12 ,  G11C7/10

Abstract: A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

公开(公告)号：US20190214084A1

公开(公告)日：2019-07-11

申请号：US16139762

申请日：2018-09-24

Applicant: SK hynix Inc.

Inventor： Ki Won LEE ,  Jung Hyuk YOON

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  H01L27/2463

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

公开(公告)号：US20210264979A1

公开(公告)日：2021-08-26

申请号：US16933636

申请日：2020-07-20

Applicant: SK hynix Inc.

Inventor： Ki Myung KYUNG ,  Jung Hyuk YOON ,  Ki Won LEE

IPC: G11C13/00

Abstract: A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group.

公开(公告)号：US20200027505A1

公开(公告)日：2020-01-23

申请号：US16296796

申请日：2019-03-08

Applicant: SK hynix Inc.

Inventor： Ki Won LEE ,  Seok Man HONG ,  Tae Hoon KIM ,  Hyung Dong LEE

IPC: G11C13/00

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

公开(公告)号：US20180287613A1

公开(公告)日：2018-10-04

申请号：US15844060

申请日：2017-12-15

Applicant: SK hynix Inc.

Inventor： Ki Won LEE

IPC: H03K19/0185

Abstract: A semiconductor device may be provided. The semiconductor device may include a first input signal-inverting circuit, a second input signal-inverting circuit, a first level-shifting circuit and a second level-shifting circuit. The first input signal-inverting circuit may be configured to invert and output an input signal. The second input signal-inverting circuit may be configured to invert and output an output signal from the first input signal-inverting circuit. The first level-shifting circuit may be configured to determine a voltage level of a first output node in response to the output signals from the first and second input signal-inverting circuits. The second level-shifting circuit may be configured to determine a voltage level of a second output node in response to the output signals from the first and second input signal-inverting circuits.

公开(公告)号：US20180150245A1

公开(公告)日：2018-05-31

申请号：US15463087

申请日：2017-03-20

Applicant: SK hynix Inc.

Inventor： Jeen PARK ,  Ki Won LEE

IPC: G06F3/06 ,  G06F1/28 ,  G06F11/10

CPC classification number: G06F3/0619 ,  G06F1/28 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1004

Abstract: A data processing system includes a host device; and a data storage device suitable for detecting a voltage drop state in the voltage received from the host device, changing a first key received from the host device to a second key when detecting the voltage drop state, generating a cyclical redundancy check (CRC) data based on the second key, and transmitting the generated CRC data to the host device.

公开(公告)号：US20210104277A1

公开(公告)日：2021-04-08

申请号：US17123830

申请日：2020-12-16

Applicant: SK hynix Inc.

Inventor： Ki Won LEE ,  Jung Hyuk YOON

IPC: G11C13/00 ,  G11C8/06 ,  H01L27/24

Abstract: A variably resistive memory device may include a memory cell array and a control circuit block. The memory cell array may include a plurality of word lines, a plurality of bit lines and a plurality of memory cells. The memory cell array may also include memory layers connected between the word lines and the bit lines. The control circuit block may include a read/write circuit and a bit line control circuit. The read/write circuit may be configured to provide a selected bit line among the plurality of bit lines with a read voltage or a write voltage. The bit line control circuit may be connected with the read/write circuit and the bit lines to control a bit line voltage inputted into the selected bit line based on a location at which a selected memory cell is electrically connected to the selected bit line.

公开(公告)号：US20200327939A1

公开(公告)日：2020-10-15

申请号：US16715343

申请日：2019-12-16

Applicant: SK hynix Inc.

Inventor： Ki Won LEE ,  Jin Su PARK

IPC: G11C13/00 ,  H01L27/24

Abstract: A resistance variable memory device may include a plurality of memory cells and a control circuit block. The memory cells may be connected between a global word line and a global bit line. The control circuit block may control the memory cells. The control circuit block may include a write pulse control block. The write pulse control block may include a high resistance path circuit and a bypass circuit connected between the global word line and a selected memory cell. The write pulse control block may selectively enable any one of the high resistance path circuit and the bypass circuit in accordance with a position the selected memory cell.