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公开(公告)号：US20240251687A1
公开(公告)日：2024-07-25
申请号：US18590813
申请日：2024-02-28
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
CPC classification number: H10N70/841 , H10B61/00 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/011 , H10N70/231
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US20220059503A1
公开(公告)日：2022-02-24
申请号：US17154705
申请日：2021-01-21
Applicant: SK hynix Inc.
Inventor： Tae Hoon KIM , Chae Sung LEE
IPC: H01L25/065 , H01L23/31 , H01L23/498 , H01L23/00
Abstract: A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second end portion of each vertical interconnector.
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公开(公告)号：US20160064360A1
公开(公告)日：2016-03-03
申请号：US14936301
申请日：2015-11-09
Applicant: SK hynix Inc.
Inventor： Tae Hoon KIM
IPC: H01L25/065 , H01L23/00
CPC classification number: H01L25/0657 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/91 , H01L25/50 , H01L2224/05553 , H01L2224/05599 , H01L2224/29099 , H01L2224/32145 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48106 , H01L2224/48225 , H01L2224/48229 , H01L2224/48465 , H01L2224/49176 , H01L2224/73265 , H01L2224/78301 , H01L2224/832 , H01L2224/8389 , H01L2224/85007 , H01L2224/85181 , H01L2224/852 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/8547 , H01L2224/92247 , H01L2225/0651 , H01L2225/06555 , H01L2924/00014 , H01L2924/01006 , H01L2924/1434 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad.
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4.发明公开公开(公告)号：US20240046973A1
公开(公告)日：2024-02-08
申请号：US18084547
申请日：2022-12-20
Applicant: SK hynix Inc.
Inventor： Su Il JIN , Tae Hoon KIM
IPC: G11C11/4074 , G11C11/4076 , G11C11/4099
CPC classification number: G11C11/4074 , G11C11/4076 , G11C11/4099
Abstract: An auxiliary power supply includes an auxiliary power storage configured to store power that is input to the auxiliary power supply and a control circuit, wherein the control circuit is configured to charge, for a reference time amount after the power is input to the auxiliary power supply, the auxiliary power storage by a first current source having a preset peak current level, determine, after the reference tune amount, that the auxiliary power supply is in a slow charging state when a voltage level that is charged to the auxiliary power storage by the first current source for the reference time amount is lower than a reference voltage level, and increase, in response to the slow charging state, the peak current level to charge the auxiliary power storage by a second current source having the increased peak current level that is greater than the preset peak current level.
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公开(公告)号：US20220320427A1
公开(公告)日：2022-10-06
申请号：US17847034
申请日：2022-06-22
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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Patent Agency Ranking
公开(公告)号：US20220285974A1
公开(公告)日：2022-09-08
申请号：US17461673
申请日：2021-08-30
Applicant: SK hynix Inc.
Inventor： Tae Hoon KIM , Jae Woong JEONG , Rak Hun CHOI , Eun Kyu CHOI , Tae Seung HAN
Abstract: The present technology includes a power supply and a method of operating the same. The power supply includes a main power supply configured to receive external power and output a charge voltage and main power, and an auxiliary power supply including a capacitor array configured to charge auxiliary power using the charge voltage and output the auxiliary power. The auxiliary power supply is configured to periodically repeat a discharge operation and a sub charge operation on the capacitor array when the charging of the capacitor array is started.
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7.发明申请公开(公告)号：US20210217472A1
公开(公告)日：2021-07-15
申请号：US17214592
申请日：2021-03-26
Applicant: SK hynix Inc.
Inventor： Ki Won LEE , Seok Man HONG , Tae Hoon KIM , Hyung Dong LEE
IPC: G11C13/00
Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
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公开(公告)号：US20200350008A1
公开(公告)日：2020-11-05
申请号：US16661551
申请日：2019-10-23
Applicant: SK hynix Inc.
Inventor： Hyung Dong LEE , Tae Hoon KIM
Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.
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公开(公告)号：US20190295659A1
公开(公告)日：2019-09-26
申请号：US16238688
申请日：2019-01-03
Applicant: SK hynix Inc.
Inventor： Jiman HONG , Tae Hoon KIM
Abstract: The memory controller includes a command generator generating first read commands respectively corresponding to each of a plurality of read voltages having different levels and transferring the first read commands to a memory device so that first read operation is performed plural times on a plurality of memory cells for each of the read voltages, and an inverted cell counter determining inverted cells showing different bit values during the first read operation performed plural times for each read voltage on the basis of read result data received from the memory device.
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公开(公告)号：US20150303175A1
公开(公告)日：2015-10-22
申请号：US14452305
申请日：2014-08-05
Applicant: SK Hynix Inc.
Inventor： Tae Hoon KIM
IPC: H01L25/065 , H01L23/00 , H01L25/00
CPC classification number: H01L25/0657 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/91 , H01L25/50 , H01L2224/05553 , H01L2224/05599 , H01L2224/29099 , H01L2224/32145 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/48106 , H01L2224/48225 , H01L2224/48229 , H01L2224/48465 , H01L2224/49176 , H01L2224/73265 , H01L2224/78301 , H01L2224/832 , H01L2224/8389 , H01L2224/85007 , H01L2224/85181 , H01L2224/852 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/8547 , H01L2224/92247 , H01L2225/0651 , H01L2225/06555 , H01L2924/00014 , H01L2924/01006 , H01L2924/1434 , H01L2224/45015 , H01L2924/207
Abstract: A semiconductor package includes a package substrate on which a substrate pad is disposed, a structure disposed over the package substrate, a semiconductor chip disposed over the structure using an adhesive member having a magnetic material layer disposed therein, a chip pad disposed on a top surface of the semiconductor chip, and a bonding wire coupling the substrate pad and the chip pad.
Abstract translation: 一种半导体封装，包括：衬底，其上设置有衬底焊盘的封装衬底;设置在封装衬底上的结构，使用其中设置有磁性材料层的粘合构件设置在结构上的半导体芯片;设置在顶表面上的芯片焊盘 以及连接基板焊盘和芯片焊盘的接合线。
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