公开(公告)号：US11903185B2

公开(公告)日：2024-02-13

申请号：US17560050

申请日：2021-12-22

申请人： SK hynix Inc.

发明人： Kun-Young Lee ,  Sun-Young Kim

IPC分类号： H10B12/00

CPC分类号： H10B12/373 ,  H10B12/0383 ,  H10B12/09 ,  H10B12/50

摘要： Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.

公开(公告)号：US11233060B2

公开(公告)日：2022-01-25

申请号：US16720760

申请日：2019-12-19

申请人： SK hynix Inc.

发明人： Kun-Young Lee ,  Sun-Young Kim

IPC分类号： H01L27/108

摘要： Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.

公开(公告)号：US09608077B1

公开(公告)日：2017-03-28

申请号：US15048236

申请日：2016-02-19

申请人： SK hynix Inc.

发明人： Jeong-Seob Kye ,  Jae-Sung Kim ,  Tae-Kyum Kim ,  Kun-Young Lee

IPC分类号： H01L21/82 ,  H01L29/40 ,  H01L29/45 ,  H01L21/02 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/401 ,  H01L21/02425 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/30604 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/82385 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10894 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66636

摘要： A method for manufacturing a semiconductor structure includes preparing a semiconductor substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the semiconductor substrate in the memory cell region; forming a bit line structure over the semiconductor substrate in the memory cell region; forming a dielectric layer in the peripheral circuit region and the memory cell region; forming a first opening in the dielectric layer in the memory cell region; filling a silicon filler in the first opening; forming a second opening in the dielectric layer in the peripheral circuit region; forming a sidewall spacer over a sidewall of the second opening; recessing the silicon filler to form a silicon plug, wherein the silicon plug fills a lower portion of the first opening; and forming a first metal silicide over a top surface of the silicon plug, and concurrently forming a second metal silicide in a lower portion of the second opening.