METHOD FOR MANUFACTURING MEMORY DEVICE HAVING WORD LINE SURROUNDING GATE STRUCTURE

    公开(公告)号:US20240023322A1

    公开(公告)日:2024-01-18

    申请号:US18218210

    申请日:2023-07-05

    发明人: SZU-YAO CHANG

    IPC分类号: H10B12/00

    摘要: The present application provides a memory device having a word line (WL) surrounding a gate structure and a manufacturing method of the memory device. The memory device includes a first dielectric surrounding a capacitor; a second dielectric disposed over the first dielectric and the capacitor; a word line embedded in the second dielectric; and a gate structure disposed over the capacitor and extending through the second dielectric, wherein the gate structure is at least partially surrounded by the word line.

    Array of capacitors, an array of memory cells, a method of forming an array of capacitors, and a method of forming an array of memory cells

    公开(公告)号:US11744061B2

    公开(公告)日:2023-08-29

    申请号:US17159719

    申请日:2021-01-27

    IPC分类号: H10B12/00

    CPC分类号: H10B12/0383 H10B12/37

    摘要: A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

    Vertical non-volatile memory devices having a multi-stack structure with enhanced photolithographic alignment characteristics

    公开(公告)号:US11895827B2

    公开(公告)日:2024-02-06

    申请号:US17469469

    申请日:2021-09-08

    IPC分类号: H10B12/00

    摘要: A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.

    Array of memory cells
    4.
    发明授权

    公开(公告)号:US11877438B2

    公开(公告)日:2024-01-16

    申请号:US18076888

    申请日:2022-12-07

    发明人: Antonino Rigano

    摘要: A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above and directly against a first capacitor electrode material. A mask is used to subtractively etch both the transistor material and thereafter the first capacitor electrode material to form a plurality of pillars that individually comprise the transistor material and the first capacitor electrode material. Capacitors are formed that individually comprise the first capacitor electrode material of individual of the pillars. Vertical transistors are formed above the capacitors that individually comprise the transistor material of the individual pillars. Other aspects and embodiments are disclosed, including structure independent of method.

    Semiconductor structure and method of manufacturing the same

    公开(公告)号:US11948969B2

    公开(公告)日:2024-04-02

    申请号:US17461308

    申请日:2021-08-30

    IPC分类号: H10B12/00 H01L49/02

    摘要: A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.

    MEMORY DEVICES HAVING VERTICAL TRANSISTORS AND METHODS FOR FORMING THE SAME

    公开(公告)号:US20230380136A1

    公开(公告)日:2023-11-23

    申请号:US18222886

    申请日:2023-07-17

    IPC分类号: H10B12/00

    CPC分类号: H10B12/0383 H10B12/50

    摘要: A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

    Vertical memory device
    10.
    发明授权

    公开(公告)号:US11903185B2

    公开(公告)日:2024-02-13

    申请号:US17560050

    申请日:2021-12-22

    申请人: SK hynix Inc.

    IPC分类号: H10B12/00

    摘要: Disclosed is a vertically stacked 3D memory device, and the memory device may include a bit line extended vertically from a substrate, and including a first vertical portion and a second vertical portion, a vertical active layer configured to surround the first and second vertical portions of the bit line, a word line configured to surround the vertical active layer and the first vertical portion of the bit line, and a capacitor spaced apart vertically from the word line, and configured to surround the vertical active layer and the second vertical portion of the bit line.