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    Clock distribution circuit and semiconductor device including the clock distribution circuit
    3.
    发明授权
    Clock distribution circuit and semiconductor device including the clock distribution circuit 有权

    公开(公告)号：US11385674B2

    公开(公告)日：2022-07-12

    申请号：US16890717

    申请日：2020-06-02

    Applicant: SK hynix Inc.

    Inventor： Soo Young Jang ,  Dae Han Kwon ,  Geun Il Lee ,  Kyu Dong Hwang

    IPC: G06F1/10 ,  H03K19/0185 ,  H03L7/189

    Abstract: A clock distribution circuit may include a data clock generation circuit configured to be input a power source voltage and configured to generate an internal clock signal according to an external clock signal; and a global distribution circuit includes a first circuit and a second circuit coupled to a global line, configured to be input a power source voltage and configured to receive the internal clock signal through the first circuit and distribute the internal clock signal to an exterior of the clock distribution circuit through the second circuit, wherein a first bias voltage provided to the first circuit and a second bias voltage provided to the second circuit are controlled independently of each other.

    Transmitter for transmitting a duobinary signal
    4.
    发明授权
    Transmitter for transmitting a duobinary signal 有权

    公开(公告)号：US11374570B1

    公开(公告)日：2022-06-28

    申请号：US17395288

    申请日：2021-08-05

    Applicant: SK hynix Inc. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

    Inventor： Dongsuk Kang ,  Jaewoo Park ,  Jung-Hoon Chun ,  Kyu Dong Hwang ,  Dae Han Kwon

    IPC: H03K19/00 ,  H03K19/017 ,  H03K19/09 ,  H03K19/17772

    Abstract: A transmitter provides a duobinary signal corresponding to one of level 0, level 1, and level 2 based on first data and second data, and includes a pull-up driving circuit including a plurality of pull-up resistors selectively coupled between a first power source and a transmission node according to the first data and the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively coupled between the transmission node and a second power source, wherein at least one of the plurality of pull-up resistors is coupled between the first power source and the transmission node both when the first data is activated and when the second data is activated, or at least one of the plurality of pull-down resistors is coupled between the second power source and the transmission node both when the first data is activated and when the second data is activated.

    Output control circuit and semiconductor apparatus including the same
    5.
    发明授权
    Output control circuit and semiconductor apparatus including the same 有权

    公开(公告)号：US11327911B2

    公开(公告)日：2022-05-10

    申请号：US16855566

    申请日：2020-04-22

    Applicant: SK hynix Inc.

    Inventor： Kyu Young Kim ,  Dae Han Kwon ,  Ha Jun Jeong

    IPC: G11C7/22 ,  G06F13/20 ,  G11C7/10

    Abstract: A semiconductor apparatus may include a data output path connected to a data input/output pad and configured to output read data according to a read command, and at least one circuit configuration included in the data output path may perform a pre-toggling operation of toggling its own output signal at least once in an interval between a time point at which the read command has been generated and a time point at which the read data is outputted through the data output path.

    Test circuit and receiving circuit having test function
    6.
    发明授权
    Test circuit and receiving circuit having test function 有权

    公开(公告)号：US12288589B2

    公开(公告)日：2025-04-29

    申请号：US18320667

    申请日：2023-05-19

    Applicant: SK hynix Inc.

    Inventor： Gi Moon Hong ,  Dae Han Kwon

    IPC: G11C29/12 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/18

    Abstract: A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09496870B2

    公开(公告)日：2016-11-15

    申请号：US14697916

    申请日：2015-04-28

    Applicant: SK hynix Inc.

    Inventor： Ic Su Oh ,  Chang Kyu Choi ,  Dae Han Kwon

    IPC: H03B1/00 ,  H03K19/00 ,  H03K3/356 ,  H03K19/0185

    CPC classification number: H03K19/0013 ,  H03K3/356104 ,  H03K3/35613 ,  H03K3/356165 ,  H03K19/018521 ,  H03K19/018571 ,  H03K19/018585

    Abstract: A semiconductor device is disclosed, which relates to a technology for reducing current consumption of a semiconductor chip configured to operate a transmitter (Tx) at a high speed. The semiconductor device includes a data driving unit configured to output a pull-up drive signal and a pull-down drive signal by level-shifting an input signal according to a clock signal; and a data output unit configured to adjust slew rates of the pull-up drive signal and the pull-down drive signal according to a code signal, and output impedance-adjusted signals to an output terminal.

    Abstract translation: 公开了一种半导体器件，其涉及用于降低被配置为以高速操作发射器（Tx）的半导体芯片的电流消耗的技术。 半导体器件包括：数据驱动单元，被配置为通过根据时钟信号对输入信号进行电平移位来输出上拉驱动信号和下拉驱动信号; 以及数据输出单元，被配置为根据代码信号调整上拉驱动信号和下拉驱动信号的转换速率，并将阻抗调整信号输出到输出端子。

    Semiconductor memory apparatus
    8.
    发明授权
    Semiconductor memory apparatus 有权

    公开(公告)号：US08867265B1

    公开(公告)日：2014-10-21

    申请号：US14301458

    申请日：2014-06-11

    Applicant: SK Hynix Inc.

    Inventor： Taek Sang Song ,  Dae Han Kwon

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C11/00 ,  G11C7/14 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

    Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

    Signal receiver and method of measuring offset of signal receiver
    10.
    发明授权
    Signal receiver and method of measuring offset of signal receiver 有权

    公开(公告)号：US11239872B2

    公开(公告)日：2022-02-01

    申请号：US17083602

    申请日：2020-10-29

    Applicant: SK hynix Inc.

    Inventor： Joo-Hyung Chae ,  Dae Han Kwon

    IPC: H04L25/34 ,  H04L25/49 ,  H04B1/12 ,  H03K5/24 ,  H04B1/16 ,  H03K3/037 ,  H04L7/00 ,  H03K5/02

    Abstract: A signal receiver includes a first preliminary receiver circuit suitable for receiving an input signal and generating a first preliminary reception signal based on a first reference voltage, a second preliminary receiver circuit suitable for receiving the input signal and generating a second preliminary reception signal based on a second reference voltage, a reception circuit suitable for selecting one of the first preliminary reception signal and the second preliminary reception signal in response to a voltage level of a reception signal and generating the reception signal using the selected signal, and a reference voltage generation circuit suitable for adjusting a voltage level of the first reference voltage based on a first offset and adjusting a voltage level of the second reference voltage based on a second offset.

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