公开(公告)号：US20220366953A1

公开(公告)日：2022-11-17

申请号：US17873730

申请日：2022-07-26

Applicant: SK hynix Inc.

Inventor： Chang Kyun PARK ,  Young Sik KOH ,  Seung Jin PARK ,  Dong Hyun LEE

IPC: G11C8/18 ,  G11C11/4076 ,  G11C7/22 ,  G11C16/32 ,  G11C7/10

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

公开(公告)号：US20210295882A1

公开(公告)日：2021-09-23

申请号：US17343027

申请日：2021-06-09

Applicant: SK hynix Inc.

Inventor： Chang Kyun PARK ,  Young Sik KOH ,  Seung Jin PARK ,  Dong Hyun LEE

IPC: G11C7/10 ,  G11C7/22

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

公开(公告)号：US20240371422A1

公开(公告)日：2024-11-07

申请号：US18773410

申请日：2024-07-15

Applicant: SK hynix Inc.

Inventor： Tae Ho LIM ,  Seung Jin PARK ,  Ie Ryung PARK ,  Dong Sop LEE

IPC: G11C7/22 ,  G11C7/10

Abstract: A data receiving circuit includes a forwarded fast clock domain configured to output data transmitted from a data transmitting circuit in synchronization with a forwarded fast clock signal, and a local clock domain configured to generate a synchronized fetch enable signal in synchronization with a local fast clock signal and output the data transmitted from the forwarded fast clock domain in synchronization with a local slow clock.

公开(公告)号：US20240177754A1

公开(公告)日：2024-05-30

申请号：US18436025

申请日：2024-02-08

Applicant: SK hynix Inc.

Inventor： Chang Kyun PARK ,  Young Sik KOH ,  Seung Jin PARK ,  Dong Hyun LEE

IPC: G11C8/18 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C16/32

CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C16/32 ,  G11C2207/2272

Abstract: A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.

公开(公告)号：US20230402073A1

公开(公告)日：2023-12-14

申请号：US17968374

申请日：2022-10-18

Applicant: SK hynix Inc.

Inventor： Sang Geun BAE ,  Seung Jin PARK

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G11C2207/2281 ,  G11C2207/2254 ,  G11C7/225

Abstract: A semiconductor system includes a first semiconductor device configured to output a clock and pattern data, configured to receive a strobe signal and output data, and configured to adjust a duty ratio of the strobe signal by comparing odd data and even data that are generated from the output data and the pattern data, in synchronization with the strobe signal and a second semiconductor device configured to store the pattern data in synchronization with the clock, configured to output the clock as the strobe signal by adjusting a duty ratio of the clock, and configured to output the stored pattern data as the output data.

公开(公告)号：US20220317933A1

公开(公告)日：2022-10-06

申请号：US17483119

申请日：2021-09-23

Applicant: SK hynix Inc.

Inventor： Soo Jin KIM ,  Seung Jin PARK

IPC: G06F3/06

Abstract: A storage device can control the input/output of data at a high frequency. The storage device includes a memory device and a memory controller for controlling the memory device, and providing the memory device with a command. The memory device includes a memory unit, and an interface chip for performing a training operation in response to the command. The interface chip generates a shift signal according to a first data strobe signal provided from the memory controller, and stores, based on the shift signal, training data provided from the memory controller.

公开(公告)号：US20210295883A1

公开(公告)日：2021-09-23

申请号：US17343046

申请日：2021-06-09

Applicant: SK hynix Inc.

Inventor： Chang Kyun PARK ,  Young Sik KOH ,  Seung Jin PARK ,  Dong Hyun LEE

IPC: G11C7/10 ,  G11C7/22

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

公开(公告)号：US20200381070A1

公开(公告)日：2020-12-03

申请号：US16727282

申请日：2019-12-26

Applicant: SK hynix Inc.

Inventor： Chang Kyun PARK ,  Young Sik KOH ,  Seung Jin PARK ,  Dong Hyun LEE

IPC: G11C29/12 ,  G11C29/44 ,  G11C29/18

Abstract: The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed.

公开(公告)号：US20160062690A1

公开(公告)日：2016-03-03

申请号：US14609177

申请日：2015-01-29

Applicant: SK hynix Inc.

Inventor： Dong Jae SHIN ,  Jong Ju PARK ,  Seung Jin PARK ,  Young Jin PARK

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F3/0625 ,  G06F1/3268 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0656 ,  G06F3/0679 ,  Y02D10/154 ,  Y02D10/171

Abstract: A data processing system includes a host device including a first memory, and a data storage device including a second memory and a third memory, and suitable for storing data to be accessed by the host device, wherein the host device requests the data storage device to upload data stored in the second memory.

Abstract translation: 数据处理系统包括主机设备，包括第一存储器和包括第二存储器和第三存储器的数据存储设备，并且适于存储要由主机设备访问的数据，其中主机设备请求数据存储设备 上传存储在第二个内存中的数据。

公开(公告)号：US20150049552A1

公开(公告)日：2015-02-19

申请号：US14092486

申请日：2013-11-27

Applicant: SK hynix Inc.

Inventor： Seung Jin PARK

IPC: G11C16/30

CPC classification number: G11C16/30 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0679 ,  G06F13/1668 ,  G11C5/143 ,  G11C7/10 ,  G11C7/222 ,  G11C16/32 ,  Y02D10/14 ,  Y02D10/154

Abstract: A data storage device includes a nonvolatile memory device; and a controller electrically coupled with the nonvolatile memory device, and configured to control an operation of the nonvolatile memory device, wherein the controller is configured to change a frequency of an internal clock and a level of an internal voltage, according to whether data is being transmitted through a channel.

Abstract translation: 数据存储装置包括非易失性存储装置; 以及与所述非易失性存储器件电耦合并且被配置为控制所述非易失性存储器件的操作的控制器，其中所述控制器被配置为根据数据是否被改变内部时钟的频率和内部电压的电平 通过一个通道传输。