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公开(公告)号：US10761747B2
公开(公告)日：2020-09-01
申请号：US15883953
申请日：2018-01-30
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Jung Hyun Kwon , Seung Gyu Jeong , Won Gyu Shin
Abstract: A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.
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公开(公告)号：US11461022B2
公开(公告)日：2022-10-04
申请号：US17222429
申请日：2021-04-05
Applicant: SK hynix Inc.
Inventor： Won Gyu Shin , Jung Hyun Kwon
Abstract: A memory system may comprise a memory; and a memory controller configured to issue, to the memory, commands scheduled in a first scheme when power consumption of the memory is less than a first threshold and commands scheduled in a second scheme when the power consumption is not less than the first threshold and less than a second threshold, and stop the issuance of the commands to the memory when the power consumption of the memory is not less than the second threshold.
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公开(公告)号：US10776262B2
公开(公告)日：2020-09-15
申请号：US16169835
申请日：2018-10-24
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Jung Hyun Kwon , Won Gyu Shin , Seung Gyu Jeong
Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.
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公开(公告)号：US11323138B1
公开(公告)日：2022-05-03
申请号：US17206632
申请日：2021-03-19
Inventor： Won Gyu Shin , Jong Sun Park , Dong Yeob Shin , Jin Ho Jeong
Abstract: Disclosed is an erasure-based Reed-Solomon code soft-decision decoding method and device, capable of reducing a decoding time while minimizing the effect on error correction performance. The Reed-Solomon code soft-decision decoding device includes an erasure control circuit configured to determine whether a number of errors in a codeword is odd or even, and to provide a key equation solver circuit with a first erasure pattern or a second erasure pattern according to a result of the determining when a decoding failure is detected by a decoding error detection circuit, the first erasure pattern being provided when the number of errors is odd, the second erasure pattern being provided when the number of errors is even.
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公开(公告)号：US11095310B2
公开(公告)日：2021-08-17
申请号：US16585564
申请日：2019-09-27
Applicant: SK hynix Inc.
Inventor： Dae Sung Kim , Won Gyu Shin
Abstract: An error correction apparatus may include: an input component configured to receive data; an error information generation component having a first error detection ability to detect L errors and a second error detection ability to detect K errors, where L is a positive integer and K is an integer larger than L, and configured to generate error information including the number of errors contained in the received data and the positions of the errors, based on the first error detection ability, and generate the error information based on the second error detection ability, when the error information is not generated on the basis of the first error detection ability; an error correction component configured to correct the errors of the received data based on the generated error information; and an output component configured to output the corrected data.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11501832B2
公开(公告)日：2022-11-15
申请号：US17205647
申请日：2021-03-18
Applicant: SK hynix Inc.
Inventor： Won Gyu Shin , Jung Hyun Kwon
Abstract: According to an embodiment, a memory system comprises a resistive memory device configured to perform a read operation and a write operation based on a command and an address, wherein the resistive memory device includes a plurality of banks each including a plurality of memory cells; and a memory controller configured to schedule a request from a host to generate the command and the address, wherein, when a time interval is less than a first time, the memory controller is configured to stop generation of the command and re-schedule the command corresponding to the request, the time interval spanning from a time of generation of a prior write command for a same memory cell to a time of generation of the command generated according to the request.
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7.发明授权公开(公告)号：US11169915B2
公开(公告)日：2021-11-09
申请号：US16821822
申请日：2020-03-17
Applicant: SK hynix Inc.
Inventor： Seung Gyu Jeong , Won Gyu Shin
IPC: G06F12/02
Abstract: A memory system includes a memory medium including a plurality of matrices and a plurality of data input/output (I/O) terminals, a row address adding circuit configured to add row address additive values to an input row address for accessing memory cells of the plurality of matrices, and a column address adding circuit configured to add column address additive values to an input column address for accessing to memory cells of the plurality of matrices. The plurality of matrices are configured into a plurality of matrix sub-groups, wherein each matrix sub-group includes matrices accessed through the same data I/O terminal. The row address additive values are different from each other according to the matrix sub-groups, and the column address additive values are different from each other according to the matrix sub-groups.
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公开(公告)号：US11108412B2
公开(公告)日：2021-08-31
申请号：US16726693
申请日：2019-12-24
Applicant: SK hynix Inc.
Inventor： Won Gyu Shin , Jin Woong Suh
Abstract: A memory system includes a Reed-Solomon (RS) decoder, a reliability tracking circuit, and an erasure control circuit. The RS decoder performs an error correction decoding operation of ‘K’-number of symbols outputted from a memory medium. The reliability tracking circuit generates and stores information on a reliability of the symbols, error occurrence possibilities of which are distinguished into a plurality of different levels according to the error correction decoding operation performed by the RS decoder. The erasure control circuit controls the RS decoder such that the symbols are erased in order of the reliability of the symbols from a low reliable symbol to a high reliable symbol and the error correction decoding operation is performed according to the information on the reliability of the symbols stored in the reliability tracking circuit.
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公开(公告)号：US10665297B2
公开(公告)日：2020-05-26
申请号：US16236000
申请日：2018-12-28
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Jung Hyun Kwon , Won Gyu Shin , Seung Gyu Jeong
Abstract: A memory system includes a memory device and a memory controller. The memory device has a plurality of memory regions. The memory controller is configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when the number of write commands successively generated for the first memory region reaches a reference value.
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公开(公告)号：US11824560B2
公开(公告)日：2023-11-21
申请号：US17865630
申请日：2022-07-15
Applicant: SK hynix Inc.
Inventor： Won Gyu Shin
IPC: H03M13/15
CPC classification number: H03M13/1575 , H03M13/1525 , H03M13/157 , H03M13/1545
Abstract: An ECC decoder includes a syndrome calculation block, a fast path controller, a KES block, a CSEE block, an UED, and a multiplexer. The KES block includes a plurality of KES-stages to calculate and output an error location/magnitude polynomial of a syndrome outputted from the syndrome calculation block. Each of a second to last KES-stages of the plurality of KES-stages receives the error location/magnitude polynomial from the previous KES-stage to output an error location/magnitude polynomial generated by an additional calculating operation. The additionally calculated error location/magnitude polynomial is not transmitted to the next KES-stage but directly outputted when an error location and an error magnitude are identified by the additionally calculated error location/magnitude polynomial.
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