公开(公告)号：US20250107458A1

公开(公告)日：2025-03-27

申请号：US18972831

申请日：2024-12-06

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Hyun HAN

IPC: H10N70/20

Abstract: An electronic device includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other over the substrate, a channel layer disposed between the source electrode layer and the drain electrode layer over the substrate, a proton conductive layer disposed on the channel layer, and a gate electrode layer disposed on the proton conductive layer.

公开(公告)号：US20230301208A1

公开(公告)日：2023-09-21

申请号：US17894332

申请日：2022-08-24

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Woo Cheol LEE

IPC: H01L45/00 ,  G11C13/00

CPC classification number: H01L45/06 ,  H01L45/1286 ,  H01L45/1253 ,  H01L45/1675 ,  H01L45/1616 ,  H01L45/1683 ,  G11C13/0004

Abstract: Disclosed semiconductor devices include a substrate, a device pattern structure disposed over the substrate, and a heat insulating layer disposed on the device pattern structure. The device pattern structure includes metal-organic frameworks.

公开(公告)号：US20230123138A1

公开(公告)日：2023-04-20

申请号：US17707860

申请日：2022-03-29

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Hyun HAN

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a first conductive layer including a first metal, a second conductive layer electrically connected to the first conductive layer and including a second metal, and an interconnection structure common to a connection portion of the first and second conductive layers. The interconnection structure may include a seed layer on the first conductive layer that includes graphene, and a metal migration barrier layer on the seed layer that includes MXene.

公开(公告)号：US20240081082A1

公开(公告)日：2024-03-07

申请号：US18097493

申请日：2023-01-17

Applicant: SK hynix Inc.

Inventor： Dong Ik SUH ,  Won Tae KOO

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A semiconductor device according to an embodiment includes a first electrode and a second electrode that are spaced apart from each other, a capacitor dielectric structure disposed between the first electrode and the second electrode, and a barrier dielectric layer disposed between one of the first and second electrodes and the capacitor dielectric structure. The capacitor dielectric structure may include a ferroelectric layer and a dielectric layer. The barrier dielectric layer may include a ferroelectric material.

公开(公告)号：US20230309427A1

公开(公告)日：2023-09-28

申请号：US17890899

申请日：2022-08-18

Applicant: SK hynix Inc.

Inventor： Won Tae KOO

IPC: H01L45/00

CPC classification number: H01L45/1233 ,  H01L45/1206 ,  H01L45/149

Abstract: An electronic device according to an embodiment of the present disclosure includes a substrate, a base electrode layer disposed over the substrate, first and second operating electrode layers disposed over the base electrode layer to be spaced apart from each other, a channel layer disposed between the first operating electrode layer and the second operating electrode layer over the base electrode layer, a proton conductive layer disposed over the first and second electrode layers and the channel layer, a hydrogen source layer disposed over the proton conductive layer, and a control electrode layer disposed over the hydrogen source layer.

公开(公告)号：US20230005742A1

公开(公告)日：2023-01-05

申请号：US17546617

申请日：2021-12-09

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Mir IM

IPC: H01L21/02

Abstract: In a method of treating a target film, a plurality of pattern structures with sidewall surfaces facing each other are provided. A target film is formed on the sidewalls of the plurality of pattern structures. A plurality of nanoparticles are distributed on the target thin film. The target thin film is thermally treated by irradiating laser light from upper sides of the plurality of pattern structures to the target thin film. The irradiated laser light is scattered from the plurality of nanoparticles.

公开(公告)号：US20220336497A1

公开(公告)日：2022-10-20

申请号：US17472365

申请日：2021-09-10

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Hyun HAN ,  Se Ho LEE

IPC: H01L27/11597 ,  H01L29/06

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.

公开(公告)号：US20240313073A1

公开(公告)日：2024-09-19

申请号：US18675467

申请日：2024-05-28

Applicant: SK hynix Inc.

Inventor： Jae Hyun HAN ,  Won Tae KOO

IPC: H01L29/423 ,  H01L21/28 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L29/42332 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42348 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor memory device includes a channel layer, a gate electrode spaced apart from the channel layer, a blocking insulating layer between the gate electrode and the channel layer, a tunnel insulating layer between the channel layer and the blocking insulating layer, and nano-particles spaced apart from each other between the tunnel insulating layer and the blocking insulating layer.

公开(公告)号：US20240006508A1

公开(公告)日：2024-01-04

申请号：US18057658

申请日：2022-11-21

Applicant: SK hynix Inc

Inventor： Won Tae KOO

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/78391

Abstract: A semiconductor device according to an embodiment includes a substrate having a channel region, a ferroelectric structure disposed over the channel region, and a gate electrode layer disposed on the ferroelectric structure. The ferroelectric structure includes a plurality of two-dimensional material layers disposed to have a moiré pattern.

公开(公告)号：US20230082400A1

公开(公告)日：2023-03-16

申请号：US17674833

申请日：2022-02-17

Applicant: SK hynix Inc.

Inventor： Won Tae KOO ,  Jae Hyun HAN

IPC: H01L45/00

Abstract: An electronic device includes a base element, a source electrode layer and a drain electrode layer disposed to be spaced apart from each other on the base element, a channel layer disposed between the source electrode layer and the drain electrode layer on the base element that accommodates metal ions, a metal ion conduction layer disposed on the channel layer, and a gate electrode layer disposed on the metal ion conduction layer. The channel layer includes a plurality of unit films and channel spaces between the plurality of unit films. The plurality of unit films are arranged to be parallel to a direction substantially perpendicular to a surface of the base element.