利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

22 条记录 (耗时 0.023 秒)

    Memory controller and method of operating the same for processing the failed read operation
    1.
    发明授权
    Memory controller and method of operating the same for processing the failed read operation 有权

    公开(公告)号：US11037639B2

    公开(公告)日：2021-06-15

    申请号：US16518313

    申请日：2019-07-22

    申请人： SK hynix Inc.

    发明人： Min Ho Her ,  Dong Hyun Kim ,  Seung Il Kim ,  Youn Ho Jung

    IPC分类号： G11C16/34 ,  G06F11/07 ,  G11C16/24 ,  G11C16/26

    摘要： Provided herein may be a memory controller and a method of operating the same. The memory controller may include a read operation controller configured to provide a read command to a memory device and receive read data corresponding to the read command, a read fail determiner configured to determine, based on the read data, whether a read operation has passed or failed, and to generate read information including a result of the read operation and information about performance of the read operation and a read fail processor configured to select, based on the read information, one of a read retry operation, among a plurality of read retry operations, to be performed on the selected page and an operation of setting a control time for a bit line coupled to the selected page, and to control the memory device to perform the selected operation.

    Semiconductor apparatus for detecting an edge of a signal
    2.
    发明授权
    Semiconductor apparatus for detecting an edge of a signal 有权

    公开(公告)号：US10756723B2

    公开(公告)日：2020-08-25

    申请号：US16003617

    申请日：2018-06-08

    申请人： SK hynix Inc.

    发明人： Dong Hyun Kim

    IPC分类号： H03K17/14 ,  H03K19/21 ,  H03K5/00 ,  G06F1/06 ,  H03K19/20 ,  H03K19/0175

    摘要： A semiconductor apparatus includes first and second edge detection signal generators. The first edge detection signal generator may generate a first edge detection signal by gating an input signal and its inverted signal based on a first gating control signal, generated by delaying the input signal, and output the first edge detection signal to an output node. The second edge detection signal generator may generate a second edge detection signal by gating a complementary signal of the input signal and its inverted signal based on a second gating control signal, generated by delaying the complementary signal, and output the second edge detection signal to the output node. An output signal may be generated at the output node.

    Noise amplification circuit and memory device including the noise amplification circuit
    5.
    发明授权
    Noise amplification circuit and memory device including the noise amplification circuit 有权

    公开(公告)号：US11100960B2

    公开(公告)日：2021-08-24

    申请号：US16733881

    申请日：2020-01-03

    申请人： SK hynix Inc.

    发明人： Kwan Su Shon ,  Dong Hyun Kim ,  Yo Han Jeong

    IPC分类号： G11C7/10 ,  G11C5/14 ,  G11C8/18 ,  G11C8/10

    摘要： A data transfer circuit and a memory device including the data transfer circuit are provided. The data transfer circuit includes a first regulator provided with an external voltage to output a first internal voltage; a second regulator configured in a same manner as the first regulator and provided with the external voltage to output a second internal voltage; an amplifier configured for amplifying noise between the first internal voltage and the second internal voltage to output an amplification voltage; and a plurality of peripheral circuits performing by being provided with the first internal voltage.

    Buffer circuit to adjust signal voltage and memory device having the same
    7.
    发明授权
    Buffer circuit to adjust signal voltage and memory device having the same 有权

    公开(公告)号：US10742181B2

    公开(公告)日：2020-08-11

    申请号：US16164187

    申请日：2018-10-18

    申请人： SK hynix Inc.

    发明人： Dong Hyun Kim ,  Eun Ji Choi ,  Yo Han Jeong ,  Jae Heung Kim

    IPC分类号： H03F3/45 ,  G11C7/10 ,  H03K19/0185

    摘要： A buffer circuit includes a first buffer configured to operate at an external power voltage, generate first and second buffer signals by comparing an input signal with a reference voltage, and control potential levels of the first and second buffer signals in response to a common mode feedback voltage; a second buffer configured to operate at an internal power voltage and generate an output signal in response to the first and second buffer signals; and a replica circuit configured to generate the common mode feedback voltage to be less than the internal power voltage.

    Delay control circuit and memory device having the same
    10.
    发明授权
    Delay control circuit and memory device having the same 有权

    公开(公告)号：US10861518B2

    公开(公告)日：2020-12-08

    申请号：US16657196

    申请日：2019-10-18

    申请人： SK hynix Inc.

    发明人： Dong Hyun Kim ,  Kwan Su Shon ,  Jin Ha Hwang

    IPC分类号： G11C7/22 ,  G11C7/10

    摘要： A delay control circuit, which may be included in a memory device, includes a delayed signal generator configured to generate an output signal by delaying an input signal in response to a delay control signal and a delay information generator configured to generate delay information indicating an output delay between the input signal and the output signal. The delay control circuit also includes a delay control signal generator configured to, based on a result of a comparison between target delay information indicating a target delay between the input signal and the output signal and based on the delay information, generate the delay control signal for controlling the output delay and fix the output delay at the target delay in response to the delay control signal.