公开(公告)号：US09646672B1

公开(公告)日：2017-05-09

申请号：US15236638

申请日：2016-08-15

Applicant: SK hynix Inc.

Inventor： Jong-Sam Kim ,  Jae-Il Kim ,  Youk-Hee Kim ,  Jun-Gi Choi ,  Hee-Seong Kim

IPC: G11C16/10 ,  G11C11/406 ,  G11C11/4091

CPC classification number: G11C11/406 ,  G11C11/40622 ,  G11C11/4091 ,  G11C16/10 ,  G11C2211/4068

Abstract: A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

公开(公告)号：US09697885B1

公开(公告)日：2017-07-04

申请号：US15298065

申请日：2016-10-19

Applicant: SK hynix Inc.

Inventor： Youk-Hee Kim

IPC: G11C11/00 ,  G11C16/10 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2211/4068

Abstract: A semiconductor memory device includes: a weak cell controller for programming weak cell information, outputting the weak cell information in response to an initialization signal or a write end signal, and outputting a read end signal whenever the weak cell information is outputted; a memory cell array region that includes memory cells for storing data in response to a row active signal and a column selection signal, and includes a first cell region for storing the weak cell information; an information transfer control circuit for generating a column address based on a column counting signal generated by using the read end signal, and generating a row address whenever the column counting signal reaches a predetermined value in response to the initialization signal; a row circuit for enabling the row active signal; and a column circuit for outputting the column selection signal by decoding the column address.

公开(公告)号：US09824776B1

公开(公告)日：2017-11-21

申请号：US15299157

申请日：2016-10-20

Applicant: SK hynix Inc.

Inventor： Youk-Hee Kim

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/40 ,  G11C11/4091 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C29/40 ,  G11C5/025 ,  G11C7/02 ,  G11C11/406 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4097 ,  G11C29/50016 ,  G11C2211/4068

Abstract: A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.

公开(公告)号：US10671477B2

公开(公告)日：2020-06-02

申请号：US15944983

申请日：2018-04-04

Applicant: SK hynix Inc.

Inventor： Youk-Hee Kim

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/06

Abstract: A method for operating a memory device includes: receiving a first read command and a first address; reading a first read data and a first error correction code from memory cells selected based on the first address; detecting and correcting an error of the first read data using the first error correction code; storing the first address as an error detection address in an address latch circuit; storing an error-corrected bit of the first read data and a position of the error-corrected bit of the first read data in a data latch circuit; and transmitting an error-corrected first read data to an external device.

公开(公告)号：US09424894B2

公开(公告)日：2016-08-23

申请号：US14505115

申请日：2014-10-02

Applicant: SK hynix Inc.

Inventor： Youk-Hee Kim ,  Yong-Ju Kim

IPC: H03K3/00 ,  G11C7/10

CPC classification number: G11C7/1078 ,  G11C7/106 ,  G11C7/1084 ,  G11C7/1087

Abstract: A signal transfer circuit includes a signal input unit suitable for generating an input signal corresponding to a first voltage level and a second voltage level, a transfer control unit suitable for controlling a driving path of a transfer node in response to a control signal and selectively driving the transfer node to the second voltage level or a third voltage level, which is higher than the first voltage level, based on the driving path in response to the input signal, and an output control unit suitable for outputting an output signal by driving an output node based on a voltage level of the transfer node or maintaining a previous voltage level of the output node in response to the control signal.

Abstract translation: 信号传输电路包括适于产生对应于第一电压电平和第二电压电平的输入信号的信号输入单元，适于响应于控制信号控制传输节点的驱动路径并选择性驱动的传送控制单元 基于响应于输入信号的驱动路径而将传输节点转换到第二电压电平或高于第一电压电平的第三电压电平，以及输出控制单元，其适于通过驱动输出来输出输出信号 基于传输节点的电压电平或者响应于控制信号保持输出节点的先前电压电平。