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    Semiconductor system and method for testing semiconductor device
    5.
    发明授权
    Semiconductor system and method for testing semiconductor device 有权
    半导体装置半导体系统及其测试方法

    公开(公告)号：US09390815B1

    公开(公告)日：2016-07-12

    申请号：US14743932

    申请日：2015-06-18

    Applicant: SK hynix Inc.

    Inventor： Sang-Ah Hyun ,  Jae-Il Kim

    IPC: G11C29/00 ,  G11C7/00 ,  G11C29/12 ,  G11C11/408 ,  G11C11/4096

    CPC classification number: G11C29/1201 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/42 ,  G11C2029/0411

    Abstract: A semiconductor system includes a semiconductor device comprising: a plurality of first input pins suitable for receiving a plurality of command/address signals; a plurality of multi-purpose registers; and a parity check unit suitable for determining a parity check result as a pass when the number of first logic values in the command/address signals corresponds to a logic value of a parity bit, determining the parity check result as a fail when the number of the first logic values does not correspond to the logic value of the parity bit, and controlling the command/address signals to be stored in the multi-purpose registers; and a function test device suitable for applying the command/address signals to the first input pins during a function test, and controlling the command/address signals such that the number of the first logic values does not correspond to the logic value of the parity bit.

    Abstract translation: 半导体系统包括半导体器件，包括：适于接收多个命令/地址信号的多个第一输入引脚; 多个多用途寄存器; 以及当命令/地址信号中的第一逻辑值的数量对应于奇偶校验位的逻辑值时，适合于将奇偶校验结果确定为奇偶校验结果的奇偶校验单元，当奇偶校验结果的数目为 第一逻辑值不对应于奇偶校验位的逻辑值，并且控制要存储在多用途寄存器中的命令/地址信号; 以及功能测试装置，其适于在功能测试期间将命令/地址信号施加到第一输入引脚，并且控制命令/地址信号使得第一逻辑值的数量不对应于奇偶校验位的逻辑值 。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US09627096B2

    公开(公告)日：2017-04-18

    申请号：US14854990

    申请日：2015-09-15

    Applicant: SK hynix Inc.

    Inventor： No-Guen Joo ,  Do-Hong Kim ,  Jae-Il Kim

    IPC: G11C11/406 ,  G11C29/00

    CPC classification number: G11C29/783 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40618

    Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.

    Semiconductor apparatus and semiconductor system including the same, and method of operating the same
    7.
    发明授权
    Semiconductor apparatus and semiconductor system including the same, and method of operating the same 有权
    包括其的半导体装置和半导体系统及其操作方法

    公开(公告)号：US09374096B2

    公开(公告)日：2016-06-21

    申请号：US14444725

    申请日：2014-07-28

    Applicant: SK hynix Inc.

    Inventor： Ga-Ram Park ,  Jae-Il Kim

    IPC: G11C7/22 ,  H03K21/02

    CPC classification number: H03K21/026 ,  G11C7/222 ,  H03K21/023

    Abstract: A semiconductor apparatus includes a clock division block suitable for generating a first internal clock and a second internal clock having a first phase difference at which active sections of the first internal clock and the second internal clock overlap with each other by dividing a phase of a source clock at a predetermined rate, and a phase detection block suitable for outputting detection result information generated by combining a result obtained by detecting a phase of the first internal clock at a predetermined edge of a strobe signal and a result obtained by detecting a phase of the second internal clock at the predetermined edge of the strobe signal.

    Abstract translation: 半导体装置包括适于产生第一内部时钟的时钟分割块和具有第一相位差的第二内部时钟，第一内部时钟和第二内部时钟的有效部分之间通过将源的相位相除 时钟，以及相位检测块，适合于输出检测结果信息，该检测结果信息通过组合通过检测选通信号的预定边缘处的第一内部时钟的相位而获得的结果，以及通过检测 第二内部时钟在选通信号的预定边缘。

    Memory device and memory system including the same
    8.
    发明授权
    Memory device and memory system including the same 有权
    存储器件和存储器系统包括相同的

    公开(公告)号：US09349430B2

    公开(公告)日：2016-05-24

    申请号：US14567706

    申请日：2014-12-11

    Applicant: SK hynix Inc.

    Inventor： Sang-Ah Hyun ,  Jae-Il Kim

    IPC: G11C11/406 ,  G11C11/408 ,  G11C8/00 ,  G11C8/12 ,  G11C11/4076

    CPC classification number: G11C11/406 ,  G11C8/04 ,  G11C8/12 ,  G11C11/40611 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4076 ,  G11C11/408

    Abstract: A memory device includes: a plurality of memory blocks; an address counting block suitable for generating a counting address that is changed when all the memory blocks are refreshed; a target address generation block suitable for generating a target address, which is an address of a word line requiring an additional refresh operation, in the memory blocks; and a refresh control block suitable for controlling a 1st number of the memory blocks to be refreshed when a refresh command is inputted a 1st number of times and controlling a 2nd number of the memory blocks to be refreshed when the refresh command is inputted a 2nd number of times, wherein the refresh control block controls a word line corresponding to the counting address to be refreshed and controls a word line corresponding to the target address to be refreshed during a target refresh operation.

    Abstract translation: 存储器件包括：多个存储器块; 地址计数块，适用于产生当所有存储块被刷新时改变的计数地址; 适于产生目标地址的目标地址生成块，所述目标地址是需要附加刷新操作的字线的地址; 以及刷新控制块，其适于在刷新命令被输入第一次时控制要刷新的第一数量的存储块，并且当刷新命令被输入时控制要刷新的第二数量的存储块数第二个数 的时间，其中刷新控制块控制与要刷新的计数地址对应的字线，并且在目标刷新操作期间控制与要刷新的目标地址相对应的字线。

    Memory device with advanced refresh scheme
    9.
    发明授权
    Memory device with advanced refresh scheme 有权
    具有高级刷新方案的内存设备

    公开(公告)号：US09548099B2

    公开(公告)日：2017-01-17

    申请号：US14542129

    申请日：2014-11-14

    Applicant: SK hynix Inc.

    Inventor： No-Guen Joo ,  Jae-Il Kim

    IPC: G11C11/406 ,  G11C11/408 ,  G11C11/4091

    CPC classification number: G11C11/406 ,  G11C11/408 ,  G11C11/4091

    Abstract: A memory device includes a counter suitable for counting the number of times that a periodic wave is enabled and generating a code, one or more memory banks each including a plurality of word lines, and one or more measurement blocks corresponding to the memory banks, respectively, and suitable for measuring an active period of an activated word line in a corresponding memory bank among the memory banks, wherein each of the measurement blocks measures the active period of the activated word line based on a first value of the code at an activation starting point of the corresponding memory bank and a current value of the code.

    Abstract translation: 一种存储装置包括一个计数器，它适用于对周期波被启用的次数进行计数，并产生一个代码，一个或多个存储器组，每个包含多个字线，以及一个或多个对应于存储体的测量块 并且适于测量存储体之间的对应存储体中的激活字线的有效周期，其中每个测量块基于激活开始时的代码的第一值来测量激活字线的有效周期 点对应的存储体和代码的当前值。

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09190128B2

    公开(公告)日：2015-11-17

    申请号：US14487974

    申请日：2014-09-16

    Applicant: SK hynix Inc.

    Inventor： Ga-Ram Park ,  Jae-Il Kim

    IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/22 ,  G11C7/02 ,  G11C7/1054 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/107

    Abstract: A semiconductor device includes a first buffer suitable for receiving and buffering data, a second buffer suitable for receiving and buffering a data strobe signal, a strobe line suitable for transferring the data strobe signal; a plurality of data transfer lines suitable for transferring data inputted at corresponding turns among data inputted in series through the first buffer, a latch signal generation block suitable for generating a plurality of latch signals which are sequentially activated, based on the data strobe signal transferred through the strobe line, a data latch block suitable for latching and aligning in parallel the data inputted in series through the first buffer, based on the latch signals, and a data transfer block suitable for transferring the data latched by the data latch block to the plurality of data transfer lines, according to a correspondence relationship determined based on an input start signal that is activated at a time when the input of data corresponding to the data input command is started.

    Abstract translation: 半导体器件包括适于接收和缓冲数据的第一缓冲器，适于接收和缓冲数据选通信号的第二缓冲器，适于传送数据选通信号的选通线; 多个数据传输线路，适于传送通过第一缓冲器串行输入的数据中相应的匝数输入的数据;锁存信号产生块，适于产生依次激活的多个锁存信号，基于通过 选通线，一个数据锁存块，适用于基于锁存信号并行地并联串行输入的数据;以及数据传输块，适用于将由数据锁存块锁存的数据传送到多个 根据在对应于数据输入命令的数据的输入开始时激活的输入开始信号确定的对应关系。

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