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6 条记录 (耗时 0.017 秒)

    TRANCEIVER CIRCUIT AND RECEIVER CIRCUIT
    1.
    发明申请
    TRANCEIVER CIRCUIT AND RECEIVER CIRCUIT 审中-公开

    公开(公告)号：US20180343028A1

    公开(公告)日：2018-11-29

    申请号：US15864092

    申请日：2018-01-08

    申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

    发明人： Deog-Kyoon JEONG ,  Han-Gon KO

    IPC分类号： H04B1/48 ,  H03K17/687 ,  H03K3/356

    摘要： A transceiver circuit may include: a first NMOS transistor suitable for pulling up a transmission line in response to a TX signal in a TX mode and for being turned on or off according to a voltage level of the transmission line in an RX mode; and a first PMOS transistor suitable for pulling down the transmission line in response to the TX signal in the TX mode and for being turned on or off according to the voltage level of the transmission line in the RX mode.

    SEMICONDUCTOR DEVICE FOR ADJUSTING PHASES OF MULTI-PHASE SIGNALS
    4.
    发明申请
    SEMICONDUCTOR DEVICE FOR ADJUSTING PHASES OF MULTI-PHASE SIGNALS 有权

    公开(公告)号：US20210167783A1

    公开(公告)日：2021-06-03

    申请号：US17027570

    申请日：2020-09-21

    申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

    发明人： Soyeong SHIN ,  Han-Gon KO ,  Deog-Kyoon JEONG

    IPC分类号： H03L7/081 ,  G06F1/10 ,  H03K5/131

    摘要： A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.

    INTEGRATED CIRCUIT AND MEMORY
    5.
    发明申请
    INTEGRATED CIRCUIT AND MEMORY 审中-公开

    公开(公告)号：US20200211605A1

    公开(公告)日：2020-07-02

    申请号：US16686941

    申请日：2019-11-18

    申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

    发明人： Deog-Kyoon JEONG ,  Han-Gon KO ,  Chan-Ho KYE ,  So-Yeong SHIN

    IPC分类号： G11C7/22 ,  G11C7/10 ,  H03L7/197 ,  H03L7/081

    摘要： An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.