公开(公告)号：US20170264308A1

公开(公告)日：2017-09-14

申请号：US15455988

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： John James DANSON ,  Ian Juso DEDIC ,  Prabhu Ashwin Harold REBELLO

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12

CPC classification number: H03M1/0675 ,  H03M1/0678 ,  H03M1/1009 ,  H03M1/1076 ,  H03M1/1215 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/38

Abstract: There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.

公开(公告)号：US20170264310A1

公开(公告)日：2017-09-14

申请号：US15455957

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Prabhu Ashwin Harold REBELLO ,  John James DANSON

IPC: H03M1/38 ,  H03M1/00 ,  H03K3/013 ,  H02M3/07 ,  H03K5/24

CPC classification number: H03M1/38 ,  H02M3/07 ,  H03K3/013 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/002

Abstract: There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.