公开(公告)号：US10593702B2

公开(公告)日：2020-03-17

申请号：US16110203

申请日：2018-08-23

Applicant: SOCIONEXT INC.

Inventor： Masaki Tamaru ,  Kazuyuki Nakanishi ,  Hidetoshi Nishimura

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

公开(公告)号：US09831271B2

公开(公告)日：2017-11-28

申请号：US15204723

申请日：2016-07-07

Applicant: Socionext Inc.

Inventor： Masaki Tamaru

IPC: H01L27/118 ,  H01L21/768 ,  H01L27/02 ,  H01L23/485 ,  H01L29/10

CPC classification number: H01L27/11807 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/1079 ,  H01L2027/11829 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

公开(公告)号：US09412757B2

公开(公告)日：2016-08-09

申请号：US14754174

申请日：2015-06-29

Applicant: SOCIONEXT INC.

Inventor： Masaki Tamaru

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/66 ,  H01L27/118 ,  H01L21/768 ,  H01L27/02 ,  H01L23/485

CPC classification number: H01L27/11807 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/1079 ,  H01L2027/11829 ,  H01L2027/11861 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

公开(公告)号：US10403644B2

公开(公告)日：2019-09-03

申请号：US15796329

申请日：2017-10-27

Applicant: Socionext Inc.

Inventor： Masaki Tamaru

IPC: H01L27/118 ,  H01L23/485 ,  H01L21/768 ,  H01L27/02 ,  H01L29/10

Abstract: A local interconnect is formed in contact with an upper surface of an impurity diffusion region and extends to below a potential supply interconnect. A contact hole electrically couples the local interconnect to the potential supply interconnect. The local interconnect, which is formed in contact with the upper surface of the impurity diffusion region, is used for electrically coupling the impurity diffusion region to the potential supply interconnect.

公开(公告)号：US10083985B2

公开(公告)日：2018-09-25

申请号：US15651818

申请日：2017-07-17

Applicant: SOCIONEXT INC.

Inventor： Masaki Tamaru ,  Kazuyuki Nakanishi ,  Hidetoshi Nishimura

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/1189

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

公开(公告)号：US09741740B2

公开(公告)日：2017-08-22

申请号：US15147656

申请日：2016-05-05

Applicant: SOCIONEXT INC.

Inventor： Masaki Tamaru ,  Kazuyuki Nakanishi ,  Hidetoshi Nishimura

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2027/11866 ,  H01L2027/11881 ,  H01L2027/1189

Abstract: A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.

公开(公告)号：US09142539B2

公开(公告)日：2015-09-22

申请号：US14574330

申请日：2014-12-17

Applicant: SOCIONEXT INC.

Inventor： Tomoaki Ikegami ,  Kazuyuki Nakanishi ,  Masaki Tamaru

IPC: H01L23/62 ,  H01L27/02 ,  H01L27/118 ,  H01L27/06

CPC classification number: H01L27/0207 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/11898

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.