SYSTEMS AND METHODS FOR MOLECULAR BONDING OF SUBSTRATES
    1.
    发明申请
    SYSTEMS AND METHODS FOR MOLECULAR BONDING OF SUBSTRATES 审中-公开
    用于分子结合基板的系统和方法

    公开(公告)号:US20150056783A1

    公开(公告)日:2015-02-26

    申请号:US14334328

    申请日:2014-10-03

    Applicant: Soitec

    CPC classification number: H01L21/67132 H01L21/02 H01L21/187 H01L21/76251

    Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

    Abstract translation: 一种用于将具有第一表面的第一基底结合到具有第二表面的第二基底的方法。 该方法包括以下步骤:通过至少两个支撑点保持第一基板,将第一基板和第二基板定位成使得第一表面和第二表面彼此面对,使第一基板通过在至少一个压力点 并且两个支撑点朝向第二基板的应变,使变形的第一表面和第二表面接触,并逐渐释放应变以促进基板的接合,同时最小化或避免在基板之间捕获气泡。

    Method for molecular bonding of silicon and glass substrates
    2.
    发明授权
    Method for molecular bonding of silicon and glass substrates 有权
    硅和玻璃基板的分子键合方法

    公开(公告)号:US08790993B2

    公开(公告)日:2014-07-29

    申请号:US13953679

    申请日:2013-07-29

    Applicant: SOITEC

    CPC classification number: H01L21/67132 H01L21/02 H01L21/187 H01L21/76251

    Abstract: A method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

    Abstract translation: 一种用于将具有第一表面的第一基底结合到具有第二表面的第二基底的方法。 该方法包括以下步骤:通过至少两个支撑点保持第一基板,将第一基板和第二基板定位成使得第一表面和第二表面彼此面对,使第一基板通过在至少一个压力点 并且两个支撑点朝向第二基板的应变,使变形的第一表面和第二表面接触,并逐渐释放应变以促进基板的接合,同时最小化或避免在基板之间捕获气泡。

    Process for thinning the active silicon layer of a substrate of “silicon on insulator” (SOI) type
    3.
    发明授权
    Process for thinning the active silicon layer of a substrate of “silicon on insulator” (SOI) type 有权
    用于使“绝缘体上硅”(SOI)型衬底的有源硅层变薄的工艺

    公开(公告)号:US09082819B2

    公开(公告)日:2015-07-14

    申请号:US14382738

    申请日:2013-01-30

    Applicant: Soitec

    Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

    Abstract translation: 本发明涉及一种用于减薄衬底的有源硅层的方法,其包括在有源层和支撑体之间的绝缘体层,该工艺包括通过牺牲热处理形成牺牲氧化层的有源层的牺牲薄化步骤 牺牲氧化层的氧化和脱氧。 该方法值得注意的是,其包括:使用氧化等离子体在有源层上形成互补氧化物层的步骤,该层具有与氧化物层的厚度分布互补的厚度,使得氧化物的厚度之和 层和牺牲氧化硅层在处理过的衬底的表面上是恒定的,该氧化物层脱氧的步骤,以便通过均匀的厚度使活性层变薄。

    "> PROCESS FOR THINNING THE ACTIVE SILICON LAYER OF A SUBSTRATE OF
    4.
    发明申请
    PROCESS FOR THINNING THE ACTIVE SILICON LAYER OF A SUBSTRATE OF "SILICON ON INSULATOR" (SOI) TYPE 有权
    “绝缘体上的硅”(SOI)类型的衬底的活性硅层的处理方法

    公开(公告)号:US20150031190A1

    公开(公告)日:2015-01-29

    申请号:US14382738

    申请日:2013-01-30

    Applicant: Soitec

    Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer, on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

    Abstract translation: 本发明涉及一种用于减薄衬底的有源硅层的方法,其包括在有源层和支撑体之间的绝缘体层,该工艺包括通过牺牲热处理形成牺牲氧化层的有源层的牺牲薄化步骤 牺牲氧化层的氧化和脱氧。 该方法值得注意的是,其包括:在有源层上使用氧化等离子体形成互补氧化物层的步骤,该层具有与氧化物层的厚度分布相互补充的厚度, 氧化物层和牺牲氧化硅层在处理过的衬底的表面上是恒定的,该氧化物层脱氧的步骤,以便通过均匀的厚度使活性层变薄。

    Method for manufacturing a semiconductor on insulator structure having low electrical losses
    6.
    发明授权
    Method for manufacturing a semiconductor on insulator structure having low electrical losses 有权
    制造具有低电损耗的绝缘体上半导体结构的方法

    公开(公告)号:US09293473B2

    公开(公告)日:2016-03-22

    申请号:US14612772

    申请日:2015-02-03

    Applicant: Soitec

    CPC classification number: H01L27/1203 H01L21/76254 H01L29/0649

    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

    Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法,其包括由硅,氧化物层和半导体材料薄层制成的支撑衬底,以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理,然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

    PROCESS FOR MANUFACTURING A COMPOSITE STRUCTURE
    7.
    发明申请
    PROCESS FOR MANUFACTURING A COMPOSITE STRUCTURE 有权
    制造复合结构的方法

    公开(公告)号:US20160042989A1

    公开(公告)日:2016-02-11

    申请号:US14780467

    申请日:2014-03-21

    Applicant: SOITEC

    Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.

    Abstract translation: 本公开涉及一种用于制造复合结构的方法,该方法包括以下步骤:a)提供施主衬底和载体衬底; b)形成电介质层; c)形成覆盖层; d)在供体衬底中形成弱化区; e)通过具有轮廓的接触表面接合载体基底和施主基底; f)通过弱化区域破坏施主衬底,执行步骤b)和e),使得轮廓被刻划在轮廓中,并且步骤c)被执行以使覆盖层覆盖电介质层的周边表面。

    METHOD FOR MANUFACTURING A SEMICONDUCTOR ON INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES
    8.
    发明申请
    METHOD FOR MANUFACTURING A SEMICONDUCTOR ON INSULATOR STRUCTURE HAVING LOW ELECTRICAL LOSSES 审中-公开
    制造具有低电损耗的绝缘体结构的半导体的方法

    公开(公告)号:US20150171110A1

    公开(公告)日:2015-06-18

    申请号:US14612772

    申请日:2015-02-03

    Applicant: SOITEC

    CPC classification number: H01L27/1203 H01L21/76254 H01L29/0649

    Abstract: A manufacturing process for a semiconductor-on-insulator structure having reduced electrical losses and which includes a support substrate made of silicon, an oxide layer and a thin layer of semiconductor material, and a polycrystalline silicon layer interleaved between the support substrate and the oxide layer. The process includes a treatment capable of conferring high resistivity to the support substrate prior to formation of the polycrystalline silicon layer, and then conducting at least one long thermal stabilization on the structure at a temperature not exceeding 950° C. for at least 10 minutes.

    Abstract translation: 一种具有降低的电损耗的绝缘体上半导体结构的制造方法,其包括由硅,氧化物层和半导体材料薄层制成的支撑衬底,以及在支撑衬底和氧化物层之间交错的多晶硅层 。 该方法包括能够在形成多晶硅层之前赋予支撑衬底高电阻率的处理,然后在不超过950℃的温度下在结构上进行至少一个长的热稳定化至少10分钟。

    METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES
    9.
    发明申请
    METHOD FOR MOLECULAR BONDING OF SILICON AND GLASS SUBSTRATES 有权
    硅和玻璃基体的分子结合方法

    公开(公告)号:US20130309841A1

    公开(公告)日:2013-11-21

    申请号:US13953679

    申请日:2013-07-29

    Applicant: SOITEC

    CPC classification number: H01L21/67132 H01L21/02 H01L21/187 H01L21/76251

    Abstract: The present invention concerns a method for bonding a first substrate having a first surface to a second substrate having a second surface. This method includes the steps of holding the first substrate by at least two support points, positioning the first substrate and the second substrate so that the first surface and the second surface face each other, deforming the first substrate by applying between at least one pressure point and the two support points a strain toward the second substrate, bringing the deformed first surface and the second surface into contact, and progressively releasing the strain to facilitate bonding of the substrates while minimizing or avoiding the trapping of air bubbles between the substrates.

    Abstract translation: 本发明涉及一种用于将具有第一表面的第一衬底与具有第二表面的第二衬底结合的方法。 该方法包括以下步骤:通过至少两个支撑点保持第一基板,将第一基板和第二基板定位成使得第一表面和第二表面彼此面对,使第一基板通过在至少一个压力点 并且两个支撑点朝向第二基板的应变,使变形的第一表面和第二表面接触,并逐渐释放应变以促进基板的接合,同时最小化或避免在基板之间捕获气泡。

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