公开(公告)号：US20160351438A1

公开(公告)日：2016-12-01

申请号：US15159646

申请日：2016-05-19

Applicant: Soitec

Inventor： Ludovic Ecarnot ,  Nicolas Daval ,  Nadia Ben Mohamed ,  Francois Boedt ,  Carole David ,  Isabell Guerin

IPC: H01L21/762 ,  B28D5/00

CPC classification number: H01L21/76251 ,  B28D5/00 ,  H01L21/02002 ,  H01L21/76254

Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.

Abstract translation: 将被称为供体衬底的单晶衬底的层转移到接收器衬底上的方法包括：提供单晶施主衬底，具有沿晶体的第一方向取向的凹槽的衬底和包围晶体的弱区域 要转移的层，将单晶供体基板接合到接收器基板上，供体基板的与弱磁区相对的相对于待转移层的主表面在接合界面处，以及供体的分离 基底沿弱点区域。 在该方法中，施主衬底在与接收器衬底接合的主表面上具有基本上沿与第一方向不同的晶体的第二方向延伸的原子台阶阵列。

公开(公告)号：US09799549B2

公开(公告)日：2017-10-24

申请号：US14780467

申请日：2014-03-21

Applicant: Soitec

Inventor： Sebastien Kerdiles ,  Guillaume Chabanne ,  Francois Boedt ,  Aurelia Pierret ,  Xavier Schneider ,  Didier Landru

IPC: H01L21/762 ,  H01L21/02 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L21/76254 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/12 ,  H01L29/0649

Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.

公开(公告)号：US20160042989A1

公开(公告)日：2016-02-11

申请号：US14780467

申请日：2014-03-21

Applicant: SOITEC

Inventor： Sebastien Kerdiles ,  Guillaume Chabanne ,  Francois Boedt

IPC: H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/76254 ,  H01L21/02164 ,  H01L21/0217 ,  H01L27/12 ,  H01L29/0649

Abstract: The disclosure relates to a process for manufacturing a composite structure, the process comprising the following steps: a) providing a donor substrate and a carrier substrate; b) forming a dielectric layer; c) forming a covering layer; d) forming a weakened zone in the donor substrate; e) joining the carrier substrate and the donor substrate via a contact surface having an outline; f) fracturing the donor substrate via the weakened zone, steps b) and e) being executed so that the outline is inscribed in the outline, and step c) being executed so that the covering layer covers the peripheral surface of the dielectric layer.

Abstract translation: 本公开涉及一种用于制造复合结构的方法，该方法包括以下步骤：a）提供施主衬底和载体衬底; b）形成电介质层; c）形成覆盖层; d）在供体衬底中形成弱化区; e）通过具有轮廓的接触表面接合载体基底和施主基底; f）通过弱化区域破坏施主衬底，执行步骤b）和e），使得轮廓被刻划在轮廓中，并且步骤c）被执行以使覆盖层覆盖电介质层的周边表面。

公开(公告)号：US20140346639A1

公开(公告)日：2014-11-27

申请号：US14372659

申请日：2013-01-14

Applicant: Soitec

Inventor： Francois Boedt ,  Roland Brun ,  Olivier Ledoux ,  Eric Butaud

IPC: H01L21/762 ,  H01L29/36 ,  H01L21/66

CPC classification number: H01L21/76254 ,  H01L22/12 ,  H01L22/20 ,  H01L29/36

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

Abstract translation: 本发明涉及一种用于制造半导体衬底的方法，其特征在于，其包括提供包括至少一个有用硅层的至少一个施主半导体衬底; 通过检查机检查供体基板，以便检测有用层是否包含尺寸大于或等于临界尺寸的新出现的空腔，所述临界尺寸严格小于44nm; 以及制造包括供体衬底的有用层的至少一部分的半导体衬底，如果考虑尺寸大于或等于临界尺寸的空腔，则供体衬底的有用层中的空腔的密度或数量低于 或等于临界缺陷密度或数量。

公开(公告)号：US09190284B2

公开(公告)日：2015-11-17

申请号：US14397287

申请日：2013-05-01

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Carine Duret ,  Francois Boedt

IPC: H01L21/306 ,  H01L21/66 ,  H01L21/762

CPC classification number: H01L21/30604 ,  H01L21/76251 ,  H01L22/12 ,  H01L22/20

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step.

Abstract translation: 本发明涉及一种用于处理绝缘体上半导体结构的方法，该方法连续地包括一个具有小于或等于100nm的厚度的支撑衬底，电介质层和半导体层，半导体层被牺牲 氧化物层，包括在分布在结构表面上的多个点处测量牺牲氧化物层和半导体层的厚度，以便产生半导体层的厚度的映射，并且从 测量，半导体层的平均厚度，牺牲氧化物层的选择性蚀刻以暴露半导体层，并且对半导体层进行化学蚀刻，其应用，温度和/或持续时间条件被调整 作为半导体层的映射和/或平均厚度的函数，从而至少局部地薄化半导体层 在测量步骤结束时被识别为厚度的厚度的电感层。

公开(公告)号：US09082819B2

公开(公告)日：2015-07-14

申请号：US14382738

申请日：2013-01-30

Applicant: Soitec

Inventor： Francois Boedt ,  Sebastien Kerdiles

IPC: H01L21/84 ,  H01L21/02 ,  H01L21/762 ,  H01L21/66 ,  H01L21/306

CPC classification number: H01L21/76256 ,  H01L21/02019 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/7624 ,  H01L22/12 ,  H01L22/20

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract translation: 本发明涉及一种用于减薄衬底的有源硅层的方法，其包括在有源层和支撑体之间的绝缘体层，该工艺包括通过牺牲热处理形成牺牲氧化层的有源层的牺牲薄化步骤 牺牲氧化层的氧化和脱氧。 该方法值得注意的是，其包括：使用氧化等离子体在有源层上形成互补氧化物层的步骤，该层具有与氧化物层的厚度分布互补的厚度，使得氧化物的厚度之和 层和牺牲氧化硅层在处理过的衬底的表面上是恒定的，该氧化物层脱氧的步骤，以便通过均匀的厚度使活性层变薄。

公开(公告)号：US20150031190A1

公开(公告)日：2015-01-29

申请号：US14382738

申请日：2013-01-30

Applicant: Soitec

Inventor： Francois Boedt ,  Sebastien Kerdiles

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76256 ,  H01L21/02019 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/7624 ,  H01L22/12 ,  H01L22/20

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer, on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract translation: 本发明涉及一种用于减薄衬底的有源硅层的方法，其包括在有源层和支撑体之间的绝缘体层，该工艺包括通过牺牲热处理形成牺牲氧化层的有源层的牺牲薄化步骤 牺牲氧化层的氧化和脱氧。 该方法值得注意的是，其包括：在有源层上使用氧化等离子体形成互补氧化物层的步骤，该层具有与氧化物层的厚度分布相互补充的厚度， 氧化物层和牺牲氧化硅层在处理过的衬底的表面上是恒定的，该氧化物层脱氧的步骤，以便通过均匀的厚度使活性层变薄。

公开(公告)号：US09911641B2

公开(公告)日：2018-03-06

申请号：US14372659

申请日：2013-01-14

Applicant: Soitec

Inventor： Francois Boedt ,  Roland Brun ,  Olivier Ledoux ,  Eric Butaud

IPC: H01L21/762 ,  H01L21/66 ,  H01L29/36

CPC classification number: H01L21/76254 ,  H01L22/12 ,  H01L22/20 ,  H01L29/36

Abstract: The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor substrate comprising at least one useful silicon layer; inspecting the donor substrate via an inspecting machine in order to detect whether the useful layer contains emerging cavities of a size larger than or equal to a critical size, said critical size being strictly smaller than 44 nm; and manufacturing a semiconductor substrate comprising at least part of the useful layer of the donor substrate if, considering cavities of a size larger than or equal to the critical size, the density or number of cavities in the useful layer of the donor substrate is lower than or equal to a critical defect density or number.

公开(公告)号：US09768057B2

公开(公告)日：2017-09-19

申请号：US15159646

申请日：2016-05-19

Applicant: Soitec

Inventor： Ludovic Ecarnot ,  Nicolas Daval ,  Nadia Ben Mohamed ,  Francois Boedt ,  Carole David ,  Isabelle Guerin

IPC: H01L21/66 ,  H01L21/762 ,  H01L21/02 ,  B28D5/00

CPC classification number: H01L21/76251 ,  B28D5/00 ,  H01L21/02002 ,  H01L21/76254

Abstract: A method for transferring a layer from a single-crystal substrate, called a donor substrate, onto a receiver substrate, includes supplying the single-crystal donor substrate, the substrate having a notch oriented in a first direction of the crystal and a weakness region bounding the layer to be transferred, bonding of the single-crystal donor substrate onto the receiver substrate, the main surface of the donor substrate opposite to the weakness region with respect to the layer to be transferred being at the bonding interface, and detachment of the donor substrate along the weakness region. In the method, the donor substrate has, on the main surface bonded to the receiver substrate, an array of atomic steps extending essentially in a second direction of the crystal different from the first direction.

公开(公告)号：US20150118764A1

公开(公告)日：2015-04-30

申请号：US14397287

申请日：2013-05-01

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Carine Duret ,  Francois Boedt

IPC: H01L21/306 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L21/30604 ,  H01L21/76251 ,  H01L22/12 ,  H01L22/20

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising: measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step.

Abstract translation: 本发明涉及一种用于处理绝缘体上半导体结构的方法，该方法连续地包括一个具有小于或等于100nm的厚度的支撑衬底，电介质层和半导体层，半导体层被牺牲 氧化物层，包括：在分布在结构表面上的多个点处测量牺牲氧化物层和半导体层的厚度，以便产生半导体层的厚度的映射， 从测量中，半导体层的平均厚度，牺牲氧化物层的选择性蚀刻以暴露半导体层，并且对半导体层进行化学蚀刻，其应用，温度和/或持续时间条件是 作为半导体层的平均厚度和/或半导体层的平均厚度的函数进行调整，以至少局部地使半 导体层在测量步骤结束时被认为是厚厚的厚度。