公开(公告)号：US20240363601A1

公开(公告)日：2024-10-31

申请号：US18646794

申请日：2024-04-26

申请人： STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.

发明人： Zelong Yu ,  Huanhuan Yuan ,  Jian Xu ,  Soo Won Lee

IPC分类号： H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC分类号： H01L25/105 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125

摘要： The present disclosure discloses a chip package structure and a preparation method thereof. The chip package structure includes: a metal wiring layer; a first chip, wherein a front surface of the first chip is flip-chipped on a first surface of the metal wiring layer; a first molding layer coating the first chip; a second chip, wherein a front surface of the second chip is flip-chipped on a second surface of the metal wiring layer; a first metal pillar formed on the second surface of the metal wiring layer; a second molding layer coating the second chip and the first metal pillar; and a second metal pillar formed on one side that is of the second molding layer and that is far away from the metal wiring layer, wherein the second metal pillar is at least partially connected to the corresponding first metal pillar.

公开(公告)号：US20240363515A1

公开(公告)日：2024-10-31

申请号：US18646799

申请日：2024-04-26

申请人： STATS CHIPPAC SEMICONDUCTOR (JIANGYIN) CO., LTD.

发明人： Jeonghan Kim ,  Soo Won Lee ,  Jian Xu ,  Hyoungill Min ,  Ruifeng Jiang

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/13 ,  H01L25/16

CPC分类号： H01L23/49833 ,  H01L21/4803 ,  H01L23/13 ,  H01L25/16

摘要： A semiconductor package structure and a forming method therefor are disclosed. The package structure includes: an encapsulant including a first and a second surfaces that are opposite and peripheral side surfaces, wherein the first surface is provided with protruding connection terminals, and junction between the first surface and the peripheral side surfaces are provided with four top corners; a substrate including a flip-chip area, wherein the flip-chip area is provided with four corner areas corresponding to four top corners of the encapsulant; trenches positioned in the substrate in the corner areas or around the corner areas or in the four corner areas and around the four corner areas at the same time; a high-modulus first underfill layer filling four trenches and spaces between the four trenches and the first surface of the encapsulant; and a low-modulus second underfill layer filling a remaining space between the encapsulant and the substrate.