公开(公告)号：US20230326769A1

公开(公告)日：2023-10-12

申请号：US18184670

申请日：2023-03-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KyoWang KOO ,  SeoJun BAE ,  JungSub LEE

IPC: H01L21/56 ,  H01L25/00

CPC classification number: H01L21/565 ,  H01L25/50

Abstract: A method for making a semiconductor device is provided. The method includes: providing a package including: a substrate including a top surface and a bottom surface; a top electronic component mounted on the top surface of the substrate; at least one conductive pillar formed on the bottom surface of the substrate; and a protection layer attached on the bottom surface of the substrate and covering the at least one conductive pillar; providing a molding apparatus including a top chase and a bottom chase, wherein a molding material is held in the bottom chase; attaching the protection layer onto the top chase of the molding apparatus; and moving the top chase and the bottom chase close to each other to compress the molding material to cover the top electronic component on the top surface of the substrate, thereby forming a top encapsulation on the top surface of the substrate.

公开(公告)号：US20230268315A1

公开(公告)日：2023-08-24

申请号：US18165347

申请日：2023-02-07

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JiSik MOON ,  DongJun SEO ,  JungSub LEE ,  KyoWang KOO

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L23/552

CPC classification number: H01L24/94 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/552 ,  H01L2224/94

Abstract: The present application relates to a method for making semiconductor packages. The method for making semiconductor packages comprises forming a semiconductor package array, the semiconductor package array having at its first side a interconnect encasing layer; attaching an adhesive tape onto the interconnect encasing layer, wherein the adhesive layer has an adhesive layer and a base film; removing, by a laser beam, the base film of the adhesive tape at a predetermined ablation region; and singulating the semiconductor package array along the predetermined ablation regions to separate the semiconductor package array into a plurality of semiconductor packages.