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公开(公告)号：US20230326769A1
公开(公告)日：2023-10-12
申请号：US18184670
申请日：2023-03-16
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： KyoWang KOO , SeoJun BAE , JungSub LEE
CPC classification number: H01L21/565 , H01L25/50
Abstract: A method for making a semiconductor device is provided. The method includes: providing a package including: a substrate including a top surface and a bottom surface; a top electronic component mounted on the top surface of the substrate; at least one conductive pillar formed on the bottom surface of the substrate; and a protection layer attached on the bottom surface of the substrate and covering the at least one conductive pillar; providing a molding apparatus including a top chase and a bottom chase, wherein a molding material is held in the bottom chase; attaching the protection layer onto the top chase of the molding apparatus; and moving the top chase and the bottom chase close to each other to compress the molding material to cover the top electronic component on the top surface of the substrate, thereby forming a top encapsulation on the top surface of the substrate.
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2.发明公开公开(公告)号：US20240021366A1
公开(公告)日：2024-01-18
申请号：US18353863
申请日：2023-07-17
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： KyoWang KOO , MinHee JEONG
CPC classification number: H01G2/10 , H01L25/16 , H05K9/0024 , H01F27/022 , H01F41/005 , H01C7/00 , H01C17/00
Abstract: An electronic package comprises: a substrate; five-sided insulated electronic components, wherein each of the five-sided insulated electronic components comprises: a raw electronic component having a cuboid shape, wherein the raw electronic component has a bottom side at which the raw electronic component is mounted onto and connected with the substrate and five non-bottom sides; a conductive structure disposed on the bottom side of the raw electronic component; and an insulating layer disposed on the five non-bottom sides of the raw electronic component.
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公开(公告)号：US20230411304A1
公开(公告)日：2023-12-21
申请号：US18313316
申请日：2023-05-06
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： Heeyoun KIM , KyoWang KOO , Junghoon KIM , Youngsang KIM , Kyungmoon KIM
IPC: H01L23/552 , H01L21/48
CPC classification number: H01L23/552 , H01L21/4814
Abstract: A semiconductor device and a method for making the same are provided. The semiconductor device includes: a substrate including a substrate top surface and a substrate bottom surface; an electronic component mounted on the substrate top surface; a bottom encapsulant disposed on the substrate top surface and encapsulating the electronic component; a top encapsulant disposed on the bottom encapsulant; an internal shielding layer disposed between the bottom encapsulant and the top encapsulant, wherein a projection of the internal shielding layer onto the substrate top surface overlaps with the electronic component, the internal shielding layer has an internal shielding layer lateral surface, and a portion of the internal shielding layer lateral surface is exposed from the bottom encapsulant and the top encapsulant; and an external shielding layer covering the bottom encapsulant and the top encapsulant and contacting with the exposed portion of the internal shielding layer lateral surface.
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Patent Agency Ranking
公开(公告)号：US20230337369A1
公开(公告)日：2023-10-19
申请号：US18299072
申请日：2023-04-12
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： KyoWang KOO , KiCheol LEE , BoLee LIM
CPC classification number: H05K3/1225 , H01L24/83 , B23K37/06 , H01L2224/83815 , H01L2224/83192 , B23K2101/42
Abstract: A stencil mask and a stencil printing method are provided. The stencil mask includes: a non-reinforcement portion having a mask surface configured to contact a substrate surface of a substrate; and a reinforcement portion having a thickness greater than that of the non-reinforcement portion, wherein the reinforcement portion includes: an embossed surface for insertion into a cavity of substrate and configured to contact a cavity bottom surface when the stencil mask is placed onto the substrate for stencil printing; and at least one first stencil window that allows the fluid material to flow through the reinforcement portion, wherein the at least one first stencil window is aligned with the at least one printing region within the cavity when the stencil mask is placed onto the substrate for stencil printing.
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公开(公告)号：US20240343055A1
公开(公告)日：2024-10-17
申请号：US18619148
申请日：2024-03-27
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： HyunSeok PARK , KyoWang KOO , SeongKuk KIM , SeokBeom HEO
IPC: B41N1/24 , B23K1/00 , B23K1/20 , B23K101/40 , B41C1/14 , B41M1/12 , B41M1/26 , G03F7/00 , H01L23/00
CPC classification number: B41N1/248 , B23K1/0016 , B23K1/203 , B41C1/148 , B41M1/12 , B41M1/26 , G03F7/0035 , H01L24/11 , H01L24/81 , B23K2101/40 , H01L2224/1147 , H01L2224/81815
Abstract: A selective stencil mask and a stencil printing method are provided. The stencil mask is for printing a fluid material onto a substrate, and comprises: a stencil member comprising: at least one printing region each having an array of apertures that allow the fluid material to flow therethrough and deposit onto the substrate; and a blocking region configured to prevent the fluid material from flowing therethrough; and a supporting member attached to the stencil member and configured to, when the stencil mask is placed on the substrate, contact the substrate and create a gap between the stencil member and the substrate.
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公开(公告)号：US20240332209A1
公开(公告)日：2024-10-03
申请号：US18603185
申请日：2024-03-12
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： JiSik MOON , KyoWang KOO , HyunSeok PARK
IPC: H01L23/552 , H01L21/683 , H01L21/78 , H01L23/31 , H01L23/498 , H01L25/16
CPC classification number: H01L23/552 , H01L21/6836 , H01L21/78 , H01L23/3107 , H01L23/49816 , H01L25/16
Abstract: A method for forming a shielding layer to a semiconductor device, wherein the semiconductor device comprises a substrate, one or more electronic components on a front surface of the substrate, an encapsulant layer on the front surface of the substrate that covers the one or more electronic components and one or more connectors on a back surface of the substrate, the method comprising: applying a coating layer onto the back surface of the substrate to cover the one or more connectors; attaching the coating layer onto a tape to load the semiconductor device to the tape, wherein the attachment between the coating layer and the tape is stronger than the attachment between the coating layer and the back surface of the substrate as well as the one or more connectors; forming the shielding layer onto the encapsulant layer to cover the one or more electronic components; and unloading the semiconductor device from the tape, wherein the coating layer is left on the tape.
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公开(公告)号：US20240234229A1
公开(公告)日：2024-07-11
申请号：US18395641
申请日：2023-12-25
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： JiEun KWON , KyoWang KOO , HyunYoung KIM , SooBin YOO
IPC: H01L23/31 , H01L23/498
CPC classification number: H01L23/3121 , H01L23/315 , H01L23/49811
Abstract: A method for making a semiconductor device using a double side molding technology is provided. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface, wherein the second surface of the substrate is uneven; forming a coating on the second surface of the substrate such that a first surface of the coating, which is facing away from the second surface of the substrate, is even; mounting a first electronic component on the first surface of the substrate; and forming a first encapsulant on the first surface of the substrate to cover the first electronic component.
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公开(公告)号：US20230268315A1
公开(公告)日：2023-08-24
申请号：US18165347
申请日：2023-02-07
Applicant: STATS ChipPAC Pte. Ltd.
Inventor： JiSik MOON , DongJun SEO , JungSub LEE , KyoWang KOO
IPC: H01L23/00 , H01L21/683 , H01L21/78 , H01L23/552
CPC classification number: H01L24/94 , H01L21/6836 , H01L21/78 , H01L23/552 , H01L2224/94
Abstract: The present application relates to a method for making semiconductor packages. The method for making semiconductor packages comprises forming a semiconductor package array, the semiconductor package array having at its first side a interconnect encasing layer; attaching an adhesive tape onto the interconnect encasing layer, wherein the adhesive layer has an adhesive layer and a base film; removing, by a laser beam, the base film of the adhesive tape at a predetermined ablation region; and singulating the semiconductor package array along the predetermined ablation regions to separate the semiconductor package array into a plurality of semiconductor packages.
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