公开(公告)号：US10985736B2

公开(公告)日：2021-04-20

申请号：US16894640

申请日：2020-06-05

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Daniele Mangano ,  Roland Van Der Tuijn ,  Pasquale Butta′

IPC: H03K3/01 ,  H03K17/20 ,  G06F1/24 ,  H03K19/20

Abstract: An embodiment device comprises a processing circuit and IP circuitry coupled to a power supply line, wherein the IP circuitry has an IP circuitry supply threshold for IP circuitry operation. A supply monitor circuit is coupled to the power supply line to sense the voltage on the power supply line and to switch the processing circuit to a low-power mode as a result of a drop in the voltage on the power supply line. The supply monitor circuit comprises a threshold setting node and is configured to be deactivated as a result of the voltage on the power supply line dropping below a deactivation threshold level set at the threshold setting node. A threshold setting circuit is configured to apply to the threshold setting node of the supply monitor circuit the IP circuitry supply threshold as a result of the processing circuit being in the low-power mode.

公开(公告)号：US09813221B2

公开(公告)日：2017-11-07

申请号：US14531442

申请日：2014-11-03

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: H04B1/44 ,  H04L5/14 ,  H04L12/801 ,  H04W4/04 ,  G06F13/42

CPC classification number: H04L5/1415 ,  G06F13/4291 ,  H04L47/35 ,  H04W4/04 ,  Y02D70/00 ,  Y02D70/144

Abstract: A method for controlling a low-power state of a pair of serial interfaces using a pair of flow-control signal lines may include enabling a first of the flow-control lines by a first one of the interfaces for signaling a transmission request to the second interface. The method may also include, in response to the transmission request, waking up to a live state from a low-power state and enabling a second flow-control line for signaling a transmission authorization to the first interface. In response to the transmission authorization, the method may include initiating a transmission of a message to the second interface, and upon reaching an offset before the end of the message transmission, disabling the first flow-control line by the first interface. The method may also include, at the end of the message transmission, disabling the second flow-control line and going back into the low-power state.

公开(公告)号：US20190044758A1

公开(公告)日：2019-02-07

申请号：US16157428

申请日：2018-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: H04L25/02 ,  H04B10/079 ,  G06F13/40

CPC classification number: H04L25/0262 ,  G06F13/4081 ,  H04B10/0795

Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.

公开(公告)号：US20190296943A1

公开(公告)日：2019-09-26

申请号：US16440069

申请日：2019-06-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: H04L25/02 ,  H04B10/079 ,  G06F13/40

Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.

公开(公告)号：US09886380B2

公开(公告)日：2018-02-06

申请号：US15141048

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: G06F12/00 ,  G06F12/06 ,  G06F3/06 ,  G06F12/0802 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/0646 ,  G06F3/0644 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0802 ,  G06F12/1009 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/657

Abstract: A virtual memory is partitioned into virtual partitions, each partition being subdivided into virtual sub-partitions and each sub-partition corresponding to a combination of multiple sectors of identical or different sizes of a physical memory. When an allocation request is made for a virtual memory space having a given memory size, a free partition is selected, a virtual sub-partition is selected corresponding to a combination of sectors having a minimum total size covering the given memory size of the virtual memory to be allocated, and free sectors of the physical memory are selected corresponding to the selected combination. A determination is made of a correspondence table between the selected virtual partition and the initial physical addresses of the selected free sectors, and a virtual address is generated.

公开(公告)号：US20170168935A1

公开(公告)日：2017-06-15

申请号：US15141048

申请日：2016-04-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: G06F12/06 ,  G06F12/08

CPC classification number: G06F12/0646 ,  G06F3/0644 ,  G06F9/5077 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0802 ,  G06F12/1009 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/657

Abstract: A virtual memory is partitioned into virtual partitions, each partition being subdivided into virtual sub-partitions and each sub-partition corresponding to a combination of multiple sectors of identical or different sizes of a physical memory. When an allocation request is made for a virtual memory space having a given memory size, a free partition is selected, a virtual sub-partition is selected corresponding to a combination of sectors having a minimum total size covering the given memory size of the virtual memory to be allocated, and free sectors of the physical memory are selected corresponding to the selected combination. A determination is made of a correspondence table between the selected virtual partition and the initial physical addresses of the selected free sectors, and a virtual address is generated.

公开(公告)号：US10361890B2

公开(公告)日：2019-07-23

申请号：US16157428

申请日：2018-10-11

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christophe Arnal ,  Roland Van Der Tuijn

IPC: H04L7/06 ,  H04L25/02 ,  H04B10/079 ,  G06F13/40

Abstract: A method can be used for transmission of at least one packet of at least one bit over a serial link capable of taking two different states respectively associated with the two possible logical values of the at least one transmitted bit. Starting from a transmission start time of the at least one bit and up to the expiration of a first portion of a bit time associated with the at least one bit, the link is placed in one of its states depending on the logical value of the at least one bit. Upon the expiration of the first portion of this bit time, a first additional transition is generated over the link so as to place the link in its other state up to the expiration of the bit time.