公开(公告)号：US20040150024A1

公开(公告)日：2004-08-05

申请号：US10702066

申请日：2003-11-05

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Alexandre Villaret ,  Thomas Skotnicki

IPC: H01L027/108

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.

Abstract translation: 集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处 并且在基本上平行于栅极的下表面的平面中的沟道区域中。 势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定 两个单元的内存状态。

公开(公告)号：US20020135020A1

公开(公告)日：2002-09-26

申请号：US10084255

申请日：2002-02-27

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Stephane Monfray ,  Alexandre Villaret

IPC: H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113

CPC classification number: H01L29/66651 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/76281 ,  H01L21/76289 ,  H01L29/66772

Abstract: The source, drain and channel regions are produced in a silicon layer completely isolated vertically from a carrier substrate by an insulating layer, and are bounded laterally by a lateral isolation region of the shallow trench type.

Abstract translation: 源极，漏极和沟道区域通过绝缘层在垂直于载体衬底完全隔离的硅层中产生，并且通过浅沟槽类型的横向隔离区域横向限定。

公开(公告)号：US20030006431A1

公开(公告)日：2003-01-09

申请号：US10174490

申请日：2002-06-18

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Alexandre Villaret

IPC: H01L031/072

CPC classification number: H01L29/42336 ,  H01L29/788

Abstract: An integrated memory location structure includes an isolated semiconductor layer between the source region and the drain region of a transistor, and between the channel region and the control gate of the transistor. The isolated semiconductor layer includes two potential well zones separated by a potential barrier zone under the control gate of the transistor. A write circuit biases the memory location structure to confine charge carriers selectively in one of the two potential well zones. A read circuit biases the memory location structure to measure the drain current of the transistor and determine therefrom the stored logic state imposed by the position of the charges in one of the potential well zones.

Abstract translation: 集成存储器位置结构包括在晶体管的源极区域和漏极区域之间以及沟道区域和晶体管的控制栅极之间的隔离半导体层。 隔离半导体层包括由晶体管的控制栅极下方的势垒区隔开的两个势阱区。 写入电路偏置存储器位置结构以将电荷载流子选择性地限制在两个势阱区域中的一个中。 读取电路偏置存储器位置结构以测量晶体管的漏极电流，并从其中确定由电荷在一个潜在阱区中施加的存储的逻辑状态。