公开(公告)号：US20040150024A1

公开(公告)日：2004-08-05

申请号：US10702066

申请日：2003-11-05

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Alexandre Villaret ,  Thomas Skotnicki

IPC: H01L027/108

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7888

Abstract: An integrated memory circuit includes at least one memory cell formed by a single transistor whose gate (GR) has a lower face insulated from a channel region by an insulation layer containing a succession of potential wells, which are substantially arranged at a distance from the gate and from the channel region in a plane substantially parallel to the lower face of the gate. The potential wells are capable of containing an electric charge which is confined in the plane and can be controlled to move in the plane towards a first confinement region next to the source region or towards a second confinement region next to the drain region so as to define two memory states for the cell.

Abstract translation: 集成存储器电路包括由单个晶体管形成的至少一个存储单元，其栅极（GR）具有通过包含一系列势阱的绝缘层与沟道区域绝缘的下表面，绝缘层基本上布置在与栅极相距一定距离处 并且在基本上平行于栅极的下表面的平面中的沟道区域中。 势阱能够容纳限制在平面中的电荷，并且可以控制其在平面内朝向源极区域旁边的第一限制区域或靠近漏极区域的第二限制区域移动，以便限定 两个单元的内存状态。

公开(公告)号：US20030034821A1

公开(公告)日：2003-02-20

申请号：US09955926

申请日：2001-09-18

Applicant: STMicroelectronics S.A.

Inventor： Catherine Mallardeau ,  Pascale Mazoyer ,  Marc Piazza

IPC: G06F001/04

CPC classification number: H01L27/10852 ,  H01L27/10882 ,  H01L27/10888

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

Abstract translation: 提供了一种集成电路，其具有包括局部掺杂的单晶衬底中形成的结的活性组分和位于活性组分之上的至少一个无源组分。 集成电路包括分离有源部件的第一绝缘层和无源部件的放宽，以及用于将无源部件与至少一个有源部件电连接的金属端子。 金属端子形成为第一绝缘层的厚度，并且具有从一个有源部件的接合极限突出的接触表面。 在优选实施例中，无源部件是电容器。 还提供了一种制造集成电路的方法，该集成电路包括MOS晶体管和矩阵中的DRAM单元的板载存储器平面。

公开(公告)号：US20020162677A1

公开(公告)日：2002-11-07

申请号：US10136682

申请日：2002-05-01

Applicant: STMICROELECTRONICS S.A.

Inventor： Pascale Mazoyer ,  Christian Caillat

IPC: H02G003/08

CPC classification number: H01L28/40 ,  H01L21/3144 ,  H01L23/5223 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Process for fabricating a component, such as a capacitor in an integrated circuit, and integrated component, in which process and component a first electrode is in the form of a cup; a layer made of a dielectric covers at least the wall of the first electrode; a second electrode fills the cup; a first electrical connection via lies above the second electrode; and a second electrical connection via lies laterally with respect to and at a predetermined distance from the first electrode and is connected to the first electrode.

Abstract translation: 用于制造组件的方法，例如集成电路中的电容器和集成部件，其中第一电极是杯形式的工艺和部件; 由电介质覆盖的层至少覆盖第一电极的壁; 第二电极填充杯子; 第一电连接通孔位于第二电极上方; 并且第二电连接通孔相对于第一电极相对于并且距离第一电极具有预定距离横向延伸并且连接到第一电极。