公开(公告)号：US20020018367A1

公开(公告)日：2002-02-14

申请号：US09896817

申请日：2001-06-29

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: G11C016/30

CPC classification number: G11C5/143 ,  G11C16/12

Abstract: An integrated circuit having as power supply voltages a low voltage reference, a logic supply voltage reference and a high voltage reference is provided. The high voltage reference is greater than the low voltage reference and the logic supply voltage reference. The integrated circuit includes an electrically programmable non-volatile memory element, and a selection and programming circuit connected thereto. A voltage control device is connected to a power supply input node of the selection and programming circuit for applying, based upon a programming control signal, the high voltage reference for programming the electrically programmable non-volatile memory element or for applying at least one logic supply voltage reference.

Abstract translation: 提供具有作为电源电压的低电压基准，逻辑电源电压基准和高电压基准的集成电路。 高电压参考值大于低电压参考电压和逻辑电源参考电压。 集成电路包括电可编程非易失性存储器元件以及与其连接的选择和编程电路。 电压控制装置连接到选择和编程电路的电源输入节点，用于基于编程控制信号将用于编程电可编程非易失性存储器元件的高电压参考值或用于施加至少一个逻辑电源 电压参考。

公开(公告)号：US20010015661A1

公开(公告)日：2001-08-23

申请号：US09727299

申请日：2000-11-30

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: G05F001/56 ,  G05F001/618

CPC classification number: G05F3/247 ,  G01R19/16519 ,  G11C5/147

Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

Abstract translation: 用于检测向集成电路的内部节点施加高电压信号的装置包括高压分压器电路和阈值检测电路。 阈值检测电路接收由分频电路的输出给出的信号，并且基于信号穿过阈值在其输出端提供阈值交叉检测信号。 检测电路连接在逻辑电源电压和地之间，并且还包括负反馈回路。 负反馈回路连接到除法器电路的输出端，以在检测阈值与信号交叉之后限制其输出处的高电压信号的电压积分。

公开(公告)号：US20030038315A1

公开(公告)日：2003-02-27

申请号：US10273925

申请日：2002-10-18

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Didier Dutartre ,  Pascal Ribot ,  Maryse Paoli ,  Richard Fournel

IPC: H01L021/336 ,  H01L029/788

CPC classification number: H01L29/66825 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42336

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract translation: 非易失性存储器包括在源极和漏极区域之间的衬底中延伸的浮动栅极。 通道区域可以被两个绝缘层限制。 本发明特别适用于使用CMOS技术的EPROM，EEPROM，闪存和单电子存储器。

公开(公告)号：US20020015345A1

公开(公告)日：2002-02-07

申请号：US09973380

申请日：2001-10-09

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: G11C007/02

CPC classification number: G11C7/12 ,  G11C16/24

Abstract: In a reading device for a memory, a circuit for the asymmetrical precharging of the differential amplifier is provided so that an output of the reading device switches over to a determined state. In the following evaluation phase, if the memory cell is programmed, the output remains unchanged. If the memory cell is blank or erased, the output of the reading device switches over to another state. A detection circuit detects a sufficient difference between the inputs of the differential amplifier for stopping the asymmetrical precharging and for making the reading device go automatically to the evaluation phase.

Abstract translation: 在用于存储器的读取装置中，提供用于差分放大器的非对称预充电的电路，使得读取装置的输出切换到确定的状态。 在以下评估阶段，如果存储单元被编程，则输出保持不变。 如果存储单元为空白或擦除，则读取装置的输出切换到另一状态。 检测电路检测用于停止非对称预充电的差分放大器的输入之间的充分差异，并使读取装置自动进入评估阶段。

公开(公告)号：US20040017702A1

公开(公告)日：2004-01-29

申请号：US10453466

申请日：2003-06-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Richard Fournel ,  Jean-Pierre Schoellkopf ,  Philippe Candelier

IPC: G11C029/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Abstract translation: 提供了几次可编程（FTP）存储元件。 FTP存储元件包括一组N个基本存储器单元和多个选择电路。 每个基本存储器单元包括用于连接到主地址总线的地址总线和用于连接到主数据总线的数据总线。 选择电路产生连续的选择信号，用于连续选择一个基本存储器单元，以给予对所选择的一个基本存储单元的独占访问。 选择电路工作，以便在检测到预定条件时自动选择下一个基本存储器单元。 在优选实施例中，每个基本存储器单元是可编程的。

公开(公告)号：US20020186599A1

公开(公告)日：2002-12-12

申请号：US10139621

申请日：2002-05-06

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Sigrid Thomas ,  Cyrille Dray

IPC: G11C007/00

CPC classification number: G11C16/0416

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the output signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

Abstract translation: 具有基于单词的组织的非易失性存储器架构包括每个字的一个选择晶体管。 该选择晶体管用于由存储器单元的源选择单词。 以这种方式，可以通过使用低电压的地址解码器的输出信号直接进行选择。 独立于该选择，高电压切换到存储器单元的栅极和漏极。 这使得能够减少所需数量的高压开关。

公开(公告)号：US20030063498A1

公开(公告)日：2003-04-03

申请号：US10228164

申请日：2002-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

公开(公告)号：US20020175353A1

公开(公告)日：2002-11-28

申请号：US10126442

申请日：2002-04-19

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray ,  Richard Fournel

IPC: H01L047/00 ,  H01L029/80

CPC classification number: G11C16/0433 ,  H01L27/115

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

Abstract translation: FAMOS存储器包括存储器单元，其中每个存储单元包括绝缘栅极晶体管，以及具有连接到绝缘栅极晶体管的源极的漏极的第一存取晶体管。 FAMOS存储器还包括绝缘晶体管，其具有分别连接到同一行的两个相邻单元的绝缘栅极晶体管的源极的漏极和源极。 每个绝缘栅极晶体管具有环形结构，并且梯形分离区域使得同一行的单元绝缘。

公开(公告)号：US20020024070A1

公开(公告)日：2002-02-28

申请号：US09895839

申请日：2001-06-29

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel

IPC: H01L029/80 ,  H01L031/112

CPC classification number: H03K17/693 ,  H03K17/102

Abstract: An integrated circuit receives as supply voltages a ground reference voltage, a logic supply voltage and a high voltage. A protection device is associated with at least one gate oxide circuit element. The protection device applies to a supply node of the circuit element either the logic supply voltage under normal conditions of operation of the integrated circuit, or the high voltage under abnormal conditions of operation of the integrated circuit for breaking down the gate oxide.

Abstract translation: 集成电路作为电源电压接收接地参考电压，逻辑电源电压和高电压。 保护装置与至少一个栅极氧化物电路元件相关联。 该保护装置在集成电路的正常工作状态下的逻辑电源电压或集成电路的异常运行状态下的高电压对电路元件的供电节点施加用于分解栅极氧化物。

公开(公告)号：US20040252554A1

公开(公告)日：2004-12-16

申请号：US10726263

申请日：2003-12-02

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Emmanuel Vincent ,  Sylvie Bruyere ,  Philippe Candelier ,  Francois Jacquet

IPC: G11C016/04

CPC classification number: G11C14/00 ,  G11C17/14

Abstract: An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18null, 20null) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18null).

Abstract translation: SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。 每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。 电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。