公开(公告)号：US09865421B2

公开(公告)日：2018-01-09

申请号：US15291962

申请日：2016-10-12

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Davide Giuseppe Patti ,  Gianleonardo Grasso

IPC: H01L29/76 ,  H01L29/94 ,  H01J9/02 ,  H01L29/78 ,  H01L29/12 ,  H01L29/66 ,  H01J21/10 ,  G01K7/01 ,  H01J1/304

CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

公开(公告)号：US09496392B2

公开(公告)日：2016-11-15

申请号：US14667215

申请日：2015-03-24

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Davide Giuseppe Patti ,  Gianleonardo Grasso

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/12 ,  H01L29/66 ,  H01J21/10 ,  G01K7/01

CPC classification number: H01J9/025 ,  G01K7/01 ,  H01J1/3044 ,  H01J21/10 ,  H01J21/105 ,  H01L29/12 ,  H01L29/66969 ,  H01L29/7827

Abstract: An integrated vacuum microelectronic structure is described as having a highly doped semiconductor substrate, a first insulating layer placed above said doped semiconductor substrate, a first conductive layer placed above said first insulating layer, a second insulating layer placed above said first conductive layer, a vacuum trench formed within said first and second insulating layers and extending to the highly doped semiconductor substrate, a second conductive layer placed above said vacuum trench and acting as a cathode, a third metal layer placed under said highly doped semiconductor substrate and acting as an anode, said second conductive layer is placed adjacent to the upper edge of said vacuum trench, the first conductive layer is separated from said vacuum trench by portions of said second insulating layer and is in electrical contact with said second conductive layer.

Abstract translation: 集成的真空微电子结构被描述为具有高度掺杂的半导体衬底，放置在所述掺杂半导体衬底之上的第一绝缘层，放置在所述第一绝缘层之上的第一导电层，放置在所述第一导电层上方的第二绝缘层，真空 形成在所述第一和第二绝缘层内并延伸到高掺杂半导体衬底的第二导电层，置于所述真空沟槽之上并用作阴极的第二导电层，置于所述高掺杂半导体衬底之下并用作阳极的第三金属层， 所述第二导电层邻近所述真空沟槽的上边缘放置，所述第一导电层通过所述第二绝缘层的一部分与所述真空沟槽分离，并与所述第二导电层电接触。