公开(公告)号：US10141422B2

公开(公告)日：2018-11-27

申请号：US15595256

申请日：2017-05-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Luisito Livellara ,  Paolo Colpani ,  Pierpaolo Monge Roffarello

IPC: H01L29/76 ,  H01L29/66 ,  H01L21/02 ,  H01L21/74 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L21/48

Abstract: A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a silicon oxide seed layer in the recess; carrying out an epitaxial growth of silicon on the substrate, simultaneously growing a polycrystalline silicon region in the seed layer and a monocrystalline silicon region in surface regions of the substrate, which surround the seed layer; and implanting dopant species in the polycrystalline silicon region to form a conductive path in order to render the second conduction terminal electrically accessible from a front side of the vertical conduction semiconductor device.

公开(公告)号：US12211754B2

公开(公告)日：2025-01-28

申请号：US17729191

申请日：2022-04-26

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierpaolo Monge Roffarello ,  Isabella Mica ,  Didier Dutartre ,  Alexandra Abbadie

IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/324 ,  H01L21/763 ,  H01L27/06

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

公开(公告)号：US20180182864A1

公开(公告)日：2018-06-28

申请号：US15595256

申请日：2017-05-15

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Luisito Livellara ,  Paolo Colpani ,  Pierpaolo Monge Roffarello

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/66734 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/265 ,  H01L21/48 ,  H01L21/743 ,  H01L23/3178 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/7802 ,  H01L29/7809

Abstract: A method of manufacturing a vertical conduction semiconductor device comprising the steps of: forming a recess in a monocrystalline silicon substrate; forming a silicon oxide seed layer in the recess; carrying out an epitaxial growth of silicon on the substrate, simultaneously growing a polycrystalline silicon region in the seed layer and a monocrystalline silicon region in surface regions of the substrate, which surround the seed layer; and implanting dopant species in the polycrystalline silicon region to form a conductive path in order to render the second conduction terminal electrically accessible from a front side of the vertical conduction semiconductor device.