公开(公告)号：US20190035741A1

公开(公告)日：2019-01-31

申请号：US16048123

申请日：2018-07-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Samuele SCIARRILLO ,  Ivan VENEGONI ,  Paolo COLPANI ,  Francesca MILANESI

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/31 ,  H01L21/768 ,  H01L23/528 ,  H01L21/308

Abstract: A semiconductor device includes a passivation layer over a dielectric layer, a via through the passivation layer and the dielectric layer, an interconnection metallization arranged over said at least one via; said passivation layer underlying peripheral portions of said interconnection metallization, and an outer surface coating that coats said interconnection metallization. The coating preferably includes at least one of a nickel or nickel alloy layer and a noble metal layer. The passivation layer is separated from the peripheral portion of the interconnection metallization by a diffusion barrier layer, preferably a titanium or a titanium alloy barrier. The device includes a dielectric layer arranged between the passivation layer and the diffusion barrier layer; and a hollow recess area between the passivation layer and the end portion of the barrier layer and between the passivation layer and the foot of the outer surface coating.

公开(公告)号：US20190035740A1

公开(公告)日：2019-01-31

申请号：US16048108

申请日：2018-07-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Samuele SCIARRILLO ,  Paolo COLPANI ,  Ivan VENEGONI

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/525 ,  H01L23/528 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/53238 ,  H01L21/76852 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02335 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/03005 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/03614 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05008 ,  H01L2224/05017 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05566 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2924/01014 ,  H01L2924/14

Abstract: A semiconductor device includes a passivation layer, an interconnection metallization 37 having a peripheral portion over the passivation layer, and an outer surface coating 37 on the interconnection metallization. A diffusion barrier layer comprises an inner planar portion directly on the surface of the passivation layer and a peripheral portion extending along a plane at a vertical height higher than the surface of the passivation layer, so that the peripheral portion forms with the inner portion a step in the barrier layer. The outer surface coating, has a vertical wall with a foot adjacent to the peripheral portion and positioned at the vertical height over the surface of the passivation layer to form a hollow recess area between the surface of the passivation layer and both of the peripheral portion and the foot of the outer surface coating.

公开(公告)号：US20230005848A1

公开(公告)日：2023-01-05

申请号：US17944983

申请日：2022-09-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Paolo COLPANI ,  Samuele SCIARRILLO ,  Ivan VENEGONI ,  Francesco Maria PIPIA ,  Simone BOSSI ,  Carmela CUPETA

IPC: H01L23/00 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.

公开(公告)号：US20200051935A1

公开(公告)日：2020-02-13

申请号：US16535029

申请日：2019-08-07

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Michele MOLGG ,  Cosimo CIMINELLI ,  Paolo COLPANI ,  Samuele SCIARRILLO ,  Ivan VENEGONI ,  Francesco Maria PIPIA ,  Simone BOSSI ,  Carmela CUPETA

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528 ,  H01L21/02

Abstract: A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.