公开(公告)号：US12170240B2

公开(公告)日：2024-12-17

申请号：US18303471

申请日：2023-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Maiden Grace Maming ,  Jefferson Sismundo Talledo

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US20190139875A1

公开(公告)日：2019-05-09

申请号：US15808680

申请日：2017-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US12074100B2

公开(公告)日：2024-08-27

申请号：US17131222

申请日：2020-12-22

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L23/49589 ,  H01L23/49548 ,  H01L23/647 ,  H01L23/49575 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US20190096788A1

公开(公告)日：2019-03-28

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.

公开(公告)号：US12159820B2

公开(公告)日：2024-12-03

申请号：US17139669

申请日：2020-12-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495 ,  H01L23/64 ,  H01L49/02

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US10892212B2

公开(公告)日：2021-01-12

申请号：US15808680

申请日：2017-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495 ,  H01L23/64 ,  H01L49/02

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US11664239B2

公开(公告)日：2023-05-30

申请号：US17317818

申请日：2021-05-11

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Maiden Grace Maming ,  Jefferson Talledo

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/562 ,  H01L24/29

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US11037864B2

公开(公告)日：2021-06-15

申请号：US16264824

申请日：2019-02-01

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Maiden Grace Maming ,  Jefferson Talledo

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US10763194B2

公开(公告)日：2020-09-01

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.