公开(公告)号：US11897763B2

公开(公告)日：2024-02-13

申请号：US17103796

申请日：2020-11-24

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Sismundo Talledo

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00309 ,  B81B7/0061 ,  B81B2201/0264 ,  B81B2201/0278 ,  B81B2207/012 ,  B81B2207/07 ,  B81C2201/0108 ,  B81C2201/0143 ,  B81C2201/0146

Abstract: A semiconductor package that contains an application-specific integrated circuit (ASIC) die and a micro-electromechanical system (MEMS) die. The MEMS die and the ASIC die are coupled to a substrate that includes an opening that extends through the substrate and is in fluid communication with an air cavity positioned between and separating the MEMS die from the substrate. The opening exposes the air cavity to an external environment and, following this, the air cavity exposes a MEMS element of the MEMS die to the external environment. The air cavity separating the MEMS die from the substrate is formed with a method of manufacturing that utilizes a thermally decomposable die attach material.

公开(公告)号：US12211772B2

公开(公告)日：2025-01-28

申请号：US17688013

申请日：2022-03-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics, Inc.

Inventor： Fulvio Vittorio Fontana ,  Davide Maria Benelli ,  Jefferson Sismundo Talledo

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device, such as a Quad-Flat No-lead (QFN) package, includes a semiconductor chip arranged on a die pad of a leadframe. The leadframe has an array of electrically-conductive leads around the die pad. The leads in the array have distal ends facing away from the die pad as well as recessed portions at an upper surface of the leads. Resilient material, such as low elasticity modulus material, is present at the upper surface of the leads and filling the recessed portions. An insulating encapsulation is molded onto the semiconductor chip. The resilient material is sandwiched between the insulating encapsulation and the distal ends of the leads. This resilient material facilitates flexibility of the leads, making them suited for reliable soldering to an insulated metal substrate.

公开(公告)号：US12170240B2

公开(公告)日：2024-12-17

申请号：US18303471

申请日：2023-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Maiden Grace Maming ,  Jefferson Sismundo Talledo

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US11610851B2

公开(公告)日：2023-03-21

申请号：US17221374

申请日：2021-04-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson Sismundo Talledo

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

公开(公告)号：US20210242112A1

公开(公告)日：2021-08-05

申请号：US17234525

申请日：2021-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo Talledo ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.

公开(公告)号：US12080657B2

公开(公告)日：2024-09-03

申请号：US18168319

申请日：2023-02-13

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo Talledo

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/351

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

公开(公告)号：US11715677B2

公开(公告)日：2023-08-01

申请号：US17234525

申请日：2021-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Sismundo Talledo ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49531 ,  H01L21/563 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/97 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4918 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45124 ,  H01L2924/00014 ,  H01L2224/45139 ,  H01L2924/00014 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.