公开(公告)号：US20190096788A1

公开(公告)日：2019-03-28

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.

公开(公告)号：US10763194B2

公开(公告)日：2020-09-01

申请号：US15713389

申请日：2017-09-22

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics Pte Ltd

Inventor： Rennier Rodriguez ,  Bryan Christian Bacquian ,  Maiden Grace Maming ,  David Gani

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683

Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.

公开(公告)号：US10109563B2

公开(公告)日：2018-10-23

申请号：US15399234

申请日：2017-01-05

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US20180190575A1

公开(公告)日：2018-07-05

申请号：US15399536

申请日：2017-01-05

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Raymond Albert Narvadez ,  Ernesto Antilano, JR.

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H05K1/11

CPC classification number: H01L23/49555 ,  H01L21/4842 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83005 ,  H01L2224/85005 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.

公开(公告)号：US12074100B2

公开(公告)日：2024-08-27

申请号：US17131222

申请日：2020-12-22

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01L23/49589 ,  H01L23/49548 ,  H01L23/647 ,  H01L23/49575 ,  H01L28/10 ,  H01L28/20 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/181 ,  H01L2924/00012

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US10957634B2

公开(公告)日：2021-03-23

申请号：US16800923

申请日：2020-02-25

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US12170240B2

公开(公告)日：2024-12-17

申请号：US18303471

申请日：2023-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Maiden Grace Maming ,  Jefferson Sismundo Talledo

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

公开(公告)号：US20190139875A1

公开(公告)日：2019-05-09

申请号：US15808680

申请日：2017-11-09

Applicant: STMICROELECTRONICS, INC.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Maiden Grace Maming

IPC: H01L23/495

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

公开(公告)号：US20190043790A1

公开(公告)日：2019-02-07

申请号：US16154538

申请日：2018-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Rennier Rodriguez ,  Aiza Marie Agudon ,  Jefferson Talledo ,  Moonlord Manalo ,  Ela Mia Cadag ,  Rammil Seguido

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.

公开(公告)号：US09761538B1

公开(公告)日：2017-09-12

申请号：US15068752

申请日：2016-03-14

Applicant: STMICROELECTRONICS, INC

Inventor： Rennier Rodriguez ,  Frederick Arellano ,  Aiza Marie Agudon

IPC: H01L21/78 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L21/4814 ,  H01L21/561 ,  H01L21/78 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81

Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.