公开(公告)号：US09368611B2

公开(公告)日：2016-06-14

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/07

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。

公开(公告)号：US20140124866A1

公开(公告)日：2014-05-08

申请号：US13853111

申请日：2013-03-29

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS S.A.

Inventor： Philippe Galy ,  Patrice Dehan ,  Boris Heitz ,  Jean Jimenez

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L27/0727 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66643 ,  H01L29/7839

Abstract: An integrated circuit may include at least one MOS transistor having a sigmoid response. The at least one MOS transistor may include a substrate, a source region, a drain region, a gate region, and insulating spacer regions on either side of the gate region. The substrate may include a first region situated under the gate region between the insulating spacer regions. At least one of the source and drain regions may be separated from the first region of the substrate by a second region of the substrate situated under an insulating spacer region, which may be of a same type of conductivity as the first region of the substrate.

Abstract translation: 集成电路可以包括具有S形响应的至少一个MOS晶体管。 至少一个MOS晶体管可以包括栅极区域的任一侧上的衬底，源极区域，漏极区域，栅极区域和绝缘间隔区域。 衬底可以包括位于绝缘间隔区之间的栅极区域下方的第一区域。 源极和漏极区域中的至少一个可以通过位于绝缘间隔区域下方的衬底的第二区域与衬底的第一区域分离，绝缘间隔区域可以具有与衬底的第一区域相同类型的导电性。

公开(公告)号：US20170179113A1

公开(公告)日：2017-06-22

申请号：US15133595

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/06 ,  H01L27/082 ,  H01L29/66 ,  H01L21/8249 ,  H01L21/8238 ,  H01L21/8228 ,  H01L27/092 ,  H01L29/808

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/823885 ,  H01L21/8249 ,  H01L27/0826 ,  H01L27/092 ,  H01L29/66909 ,  H01L29/732 ,  H01L29/8083

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

公开(公告)号：US20170194350A1

公开(公告)日：2017-07-06

申请号：US15137540

申请日：2016-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78696

Abstract: An integrated circuit includes a MOS transistor situated in and on an active region of a semiconductor substrate. The active region is bounded by an insulating region for example of the shallow trench isolation type. The drain region of the transistor is positioned in the semiconductor substrate situated away from the insulating region. An insulated gate of the transistor includes a central opening that is positioned in alignment with the drain region. A channel region of the transistor is annularly surrounds the drain region.

公开(公告)号：US10361188B2

公开(公告)日：2019-07-23

申请号：US15133595

申请日：2016-04-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez

IPC: H01L27/06 ,  H01L29/66 ,  H01L27/082 ,  H01L27/092 ,  H01L29/732 ,  H01L29/808 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8249

Abstract: An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.

公开(公告)号：US20150214210A1

公开(公告)日：2015-07-30

申请号：US14599167

申请日：2015-01-16

Applicant: STMICROELECTRONICS S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L27/0248 ,  H01L27/0262 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/7436 ,  H01L29/747

Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors

Abstract translation: 电子设备包括第一设备终端和第二设备终端。 第一和第二晶闸管反向连接在两个器件端子之间。 第一和第二MOS晶体管分别耦合在两个晶闸管的两个NPN晶体管的导通电极（发射极和集电极）之间。 第三MOS晶体管耦合在两个晶闸管的两个NPN双极晶体管的发射极之间，第四个MOS晶体管耦合在两个晶闸管的两个PNP双极晶体管的基极之间。 栅极区域对于所有MOS晶体管是公共的，并且半导体衬底区域包括所有MOS晶体管的衬底

公开(公告)号：US20140097464A1

公开(公告)日：2014-04-10

申请号：US13796753

申请日：2013-03-12

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Philippe Galy ,  Boris Heitz

IPC: H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/87

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract translation: 该组件以拓扑学方式并入具有同步环形布置的可缩放数量的三端双向可控硅结构。 该组件可与电子设备一起使用，以防止静电放电。 例如，这些组件可用于保护集成电路的输入/输出焊盘，第一电源端子和第二电源端子免受静电放电。

公开(公告)号：US20130113017A1

公开(公告)日：2013-05-09

申请号：US13628614

申请日：2012-09-27

Applicant: STMicroelectronics S.A.

Inventor： Philippe Galy ,  Jean Jimenez ,  Johan Bourgeat ,  Boris Heitz

IPC: H01L29/747

CPC classification number: H01L27/0262 ,  H01L29/747

Abstract: A protection device includes a triac and triggering units. Each triggering unit is formed by a MOS transistor configured to operate at least temporarily in a hybrid operating mode and a field-effect diode. The field-effect diode has a controlled gate that is connected to the gate of the MOS transistor.

Abstract translation: 保护装置包括三端双向可控硅开关元件和触发单元。 每个触发单元由配置成至少在混合操作模式中暂时操作的MOS晶体管和场效应二极管形成。 场效应二极管具有连接到MOS晶体管的栅极的受控栅极。

公开(公告)号：US08847275B2

公开(公告)日：2014-09-30

申请号：US13796753

申请日：2013-03-12

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Philippe Galy ,  Boris Heitz

IPC: H01L29/417 ,  H01L29/74 ,  H01L31/111 ,  H01L29/72 ,  H01L29/73 ,  H01L23/62 ,  H01L27/02 ,  H01L29/87 ,  H01L29/747

CPC classification number: H01L27/0259 ,  H01L27/0262 ,  H01L29/7436 ,  H01L29/747 ,  H01L29/87

Abstract: The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges.

Abstract translation: 该组件以拓扑学方式并入具有同步环形布置的可缩放数量的三端双向可控硅结构。 该组件可与电子设备一起使用，以防止静电放电。 例如，这些组件可用于保护集成电路的输入/输出焊盘，第一电源端子和第二电源端子免受静电放电。

公开(公告)号：US09997512B2

公开(公告)日：2018-06-12

申请号：US15199454

申请日：2016-06-30

Applicant: STMicroelectronics S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L29/00 ,  H01L27/02 ,  H01L27/12 ,  H01L27/102 ,  H01L29/74 ,  H01L29/87

CPC classification number: H01L27/0262 ,  H01L27/1027 ,  H01L27/1203 ,  H01L29/74 ,  H01L29/7408 ,  H01L29/7436 ,  H01L29/87 ,  H01L2924/1301

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.