公开(公告)号：US11996465B2

公开(公告)日：2024-05-28

申请号：US17486000

申请日：2021-09-27

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

CPC classification number: H01L29/66234 ,  H01L21/22 ,  H01L29/0649 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11296205B2

公开(公告)日：2022-04-05

申请号：US16591312

申请日：2019-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732 ,  H01L21/265

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

公开(公告)号：US11145741B2

公开(公告)日：2021-10-12

申请号：US16591371

申请日：2019-10-02

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/06 ,  H01L29/73

Abstract: A bipolar transistor includes a collector. The collector is produced by a process wherein a first substantially homogeneously doped layer is formed at the bottom of a cavity. A second gradually doped layer is then formed by diffusion of dopants of the first substantially homogeneously doped layer.

公开(公告)号：US11837647B2

公开(公告)日：2023-12-05

申请号：US17685780

申请日：2022-03-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/732 ,  H01L21/26513

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

公开(公告)号：US11251084B2

公开(公告)日：2022-02-15

申请号：US16909378

申请日：2020-06-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier ,  Gregory Avenier

IPC: H01L21/8222 ,  H01L21/265 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/737 ,  H01L29/93

Abstract: At least one bipolar transistor and at least one variable capacitance diode are jointly produced by a method on a common substrate.

公开(公告)号：US10381269B2

公开(公告)日：2019-08-13

申请号：US15911709

申请日：2018-03-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Gregory Avenier

IPC: H01L27/102 ,  H01L21/8228 ,  H01L29/423 ,  H01L29/66 ,  H01L29/732 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/311 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/082

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

公开(公告)号：US20190140072A1

公开(公告)日：2019-05-09

申请号：US15803959

申请日：2017-11-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Alexis Gauthier

IPC: H01L29/66 ,  H01L29/732 ,  H01L29/08

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector connection region. A first epitaxial region forms a collector region doped with a first conductivity type on the collector connection region. The collector region includes a counter-doped region of a second conductivity type. A second epitaxial region forms a base region of a second conductivity type on the first epitaxial region. Deposited semiconductor material forms an emitter region of the first conductivity type on the second epitaxial region. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US10224423B1

公开(公告)日：2019-03-05

申请号：US15783469

申请日：2017-10-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Pascal Chevalier ,  Gregory Avenier

IPC: H01L21/8238 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3105

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US09941170B2

公开(公告)日：2018-04-10

申请号：US15450114

申请日：2017-03-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Gregory Avenier

IPC: H01L27/102 ,  H01L21/8228 ,  H01L21/761 ,  H01L21/265 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L21/82285 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/761 ,  H01L27/0623 ,  H01L27/0716 ,  H01L27/1022 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

公开(公告)号：US20180025945A1

公开(公告)日：2018-01-25

申请号：US15450114

申请日：2017-03-06

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal Chevalier ,  Gregory Avenier

IPC: H01L21/8228 ,  H01L21/265 ,  H01L29/06 ,  H01L21/285 ,  H01L21/311 ,  H01L27/102 ,  H01L21/761 ,  H01L21/02

CPC classification number: H01L21/82285 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/31111 ,  H01L21/761 ,  H01L27/0623 ,  H01L27/0716 ,  H01L27/1022 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/42304 ,  H01L29/66272 ,  H01L29/732

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.