公开(公告)号：US11011479B2

公开(公告)日：2021-05-18

申请号：US16503876

申请日：2019-07-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/00

Abstract: An electronic chip includes a first well having a first PN junction located therein, a second buried well located under and separated from the first well, and a first region forming a second PN junction with the second well. A detection circuit is coupled to the first well and configured to output a digital signal that has a first logic value when a potential difference within the first region is above a threshold and a second logic value when the potential difference within the first region is below the threshold.

公开(公告)号：US20200020650A1

公开(公告)日：2020-01-16

申请号：US16503876

申请日：2019-07-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/00

Abstract: An electronic chip includes a first well having a first PN junction located therein, a second buried well located under and separated from the first well, and a first region forming a second PN junction with the second well. A detection circuit is coupled to the first well and configured to output a digital signal that has a first logic value when a potential difference within the first region is above a threshold and a second logic value when the potential difference within the first region is below the threshold.

公开(公告)号：US20170338824A1

公开(公告)日：2017-11-23

申请号：US15627157

申请日：2017-06-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas

IPC: H03K19/177 ,  H03K19/003 ,  H01L23/00

CPC classification number: H03K19/17768 ,  G06F21/75 ,  G06F21/87 ,  G09C1/00 ,  H01L23/576 ,  H03K19/0033 ,  H03K19/17704 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.

公开(公告)号：US11270957B2

公开(公告)日：2022-03-08

申请号：US16267573

申请日：2019-02-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/00 ,  G06F21/77 ,  G06F21/75 ,  G06K19/073

Abstract: A semiconductor substrate of an integrated circuit is protected by a coating. The semiconductor includes a front face and a rear face. To detect a breach of the integrity of a semiconductor substrate of an integrated circuit from the rear face, an opening of the coating facing the rear face of the substrate is detected. In response thereto, an alarm is generated. The detection is performed by making resistance measurements with respect to the semiconductor substrate and comparing the measured resistance to a nominal resistive value of the semiconductor substrate.

公开(公告)号：US11189578B2

公开(公告)日：2021-11-30

申请号：US16409704

申请日：2019-05-10

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas ,  Daniele Fronte

IPC: H01L23/528 ,  H01L23/00 ,  G01N27/04 ,  H01L23/522

Abstract: The disclosure concerns an electronic chip including a resistive region and a first switch of selection of a first area in contact with the resistive region.

公开(公告)号：US10063239B2

公开(公告)日：2018-08-28

申请号：US15627157

申请日：2017-06-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas

IPC: H03K19/00 ,  G01T1/24 ,  H03K19/177 ,  H01L23/00 ,  H03K19/003 ,  G06F21/75 ,  G06F21/87

CPC classification number: H03K19/17768 ,  G06F21/75 ,  G06F21/87 ,  G09C1/00 ,  H01L23/576 ,  H03K19/0033 ,  H03K19/17704 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.

公开(公告)号：US09716502B1

公开(公告)日：2017-07-25

申请号：US15379155

申请日：2016-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Bruno Nicolas

IPC: H03K19/00 ,  G01T1/24 ,  H03K19/177 ,  H01L23/00 ,  H03K19/003

CPC classification number: H03K19/17768 ,  G06F21/75 ,  G06F21/87 ,  G09C1/00 ,  H01L23/576 ,  H03K19/0033 ,  H03K19/17704 ,  H04L9/004 ,  H04L2209/12

Abstract: An integrated circuit protection device, including: groups of radiation detection elements distributed in a matrix array; logic gates combining outputs of the detection elements in rows and in columns, each output of a detection element being connected to a gate combining a row and to a gate combining a column; and a circuit for interpreting signals supplied by said logic gates and including an event counter and a delay element.