METHOD FOR CREATING AN OHMIC CONTACT ON A HIGH-POWER ELECTRICAL DIODE

    公开(公告)号:US20250015145A1

    公开(公告)日:2025-01-09

    申请号:US18348012

    申请日:2023-07-06

    Abstract: A method for forming an ohmic contact on a semiconductor component, for example a high-power electrical diode, is provided. An example method includes depositing a first metal layer on a top surface of a semiconductor drift layer having an electrical contact point, the first metal layer highly reflective of a laser light. The method further includes depositing a second metal layer on portions of the first metal layer aligned with the electrical contact point, the second metal layer selected to absorb the laser light. The method further includes exposing the first and the second metal layers to the laser light in a laser annealing process, causing the second metal layer to substantially increase in temperature due to the laser light. The increase in temperature of the second metal layer causing the ohmic contact to form between the electrical contact point and the first metal layer.

    METHODS FOR IMPROVING PASSIVATION LAYER DURABILITY

    公开(公告)号:US20250046665A1

    公开(公告)日:2025-02-06

    申请号:US18363149

    申请日:2023-08-01

    Abstract: Methods, systems, and devices for improving passivation layer durability are described. A device may include a semiconductor substrate elongated along a first direction and a second direction. The first direction may be parallel to a width of the semiconductor substrate and the second direction may be parallel to a depth of the semiconductor substrate. The device may include one or more layers formed above the semiconductor substrate with respect to a third direction parallel to a height of the semiconductor substrate. At least a region of the one or more layers may include circuitry. The device may include a passivation layer formed above the one or more layers with respect to the third direction. The passivation layer may include a plurality of cavities that each extend through the passivation layer. The plurality of cavities and the circuitry may be non-overlapping with respect to the first direction and the second direction.

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