公开(公告)号：US09245606B2

公开(公告)日：2016-01-26

申请号：US13682592

申请日：2012-11-20

Applicant: STMicroelectronics PVT LTD. ,  STMicroelectronics S.r.l.

Inventor： Danilo Rimondi ,  Carolina Selva ,  Ashish Kumar

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/413 ,  G11C7/20 ,  G11C7/22 ,  G11C29/12 ,  G11C29/24 ,  G11C11/41

CPC classification number: G11C11/00 ,  G11C7/20 ,  G11C7/227 ,  G11C11/41 ,  G11C11/413 ,  G11C29/12015 ,  G11C29/24

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract translation: 静态随机存取存储器（SRAM）装置包括多个存储单元的存储器阵列，一个接收由一连串外部脉冲形成的外部时钟信号并产生一系列内部脉冲形成的内部时钟信号的控制器，以及 一个接收内部时钟信号的驱动电路。 控制器可在第一模式下操作，其中控制器针对每个外部脉冲产生相应的内部脉冲，并且控制器控制驱动电路，使得驱动电路对每个内部脉冲执行对存储器阵列的一次访问。 控制器还可在第二模式中操作，其中控制器针对每个外部脉冲产生一对内部脉冲，并且控制器控制驱动电路，使得对于每对内部脉冲，驱动电路写入第一数据 项目，然后读取该组存储器单元，以便获取第二数据项。

公开(公告)号：US20130128656A1

公开(公告)日：2013-05-23

申请号：US13682592

申请日：2012-11-20

Applicant: STMicroelectronics PVT LTD. ,  STMicroelectronics S.r.l.

Inventor： Danilo Rimondi ,  Carolina Selva ,  Ashish Kumar

IPC: G11C11/00

CPC classification number: G11C11/00 ,  G11C7/20 ,  G11C7/227 ,  G11C11/41 ,  G11C11/413 ,  G11C29/12015 ,  G11C29/24

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract translation: 静态随机存取存储器（SRAM）装置包括多个存储单元的存储器阵列，一个接收由一连串外部脉冲形成的外部时钟信号并产生一系列内部脉冲形成的内部时钟信号的控制器，以及 一个接收内部时钟信号的驱动电路。 控制器可在第一模式下操作，其中控制器针对每个外部脉冲产生相应的内部脉冲，并且控制器控制驱动电路，使得驱动电路对每个内部脉冲执行对存储器阵列的一次访问。 控制器还可在第二模式中操作，其中控制器针对每个外部脉冲产生一对内部脉冲，并且控制器控制驱动电路，使得对于每对内部脉冲，驱动电路写入第一数据 项目，然后读取该组存储器单元，以便获取第二数据项。