公开(公告)号：US20030063498A1

公开(公告)日：2003-04-03

申请号：US10228164

申请日：2002-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

公开(公告)号：US20020176289A1

公开(公告)日：2002-11-28

申请号：US10117446

申请日：2002-04-03

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Cyrille Dray ,  Daniel Caspar

IPC: G11C007/00

CPC classification number: G11C16/0416 ,  G11C16/0408

Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

Abstract translation: FAMOS存储单元被电擦除。 可以通过向基板施加比施加到源极的电压的低至少4伏的电压和施加到漏极的电压来电存储FAMOS存储单元。 施加到基板的电压也小于预定的限制，高于该预定限度，存储单元被破坏。

公开(公告)号：US20040052148A1

公开(公告)日：2004-03-18

申请号：US10449921

申请日：2003-05-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Philippe Gendrier ,  Daniel Caspar

IPC: G11C008/02

CPC classification number: G11C17/16

Abstract: A non-volatile memory device is provided that can be irreversibly programmed electrically. The device includes a memory plane formed from a matrix of memory cells, with each of the memory cells including an access transistor and a capacitor. The memory cell matrix includes first groups of memory cells laid out in a first direction and second groups of memory cells laid out in a second direction. Each first group includes memory cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes memory cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together. The device also includes control means capable of applying chosen voltages to the first, second, and third metallizations so as to selectively program a single one of the memory cells by damaging its dielectric without programming the other memory cells and without damaging the transistors of the memory cells.

Abstract translation: 提供了可以不可逆地编程的非易失性存储器件。 该器件包括由存储器单元矩阵形成的存储器平面，每个存储器单元包括存取晶体管和电容器。 存储单元矩阵包括以第一方向布置的第一组存储器单元和沿第二方向布置的第二组存储单元。 每个第一组包括其晶体管栅极通过第一金属化连接在一起的存储单元，其上电容器电极通过第二金属化连接在一起，并且其晶体管源不连接在一起。 每个第二组包括其晶体管源通过第三金属化连接在一起的存储单元，其晶体管栅极未连接在一起，并且其上电容器电极未连接在一起。 该装置还包括能够将选择的电压施加到第一，第二和第三金属化的控制装置，以便通过损坏其电介质来选择性地编程单个存储器单元，而不对其它存储器单元进行编程，而不会损坏存储器的晶体管 细胞。