公开(公告)号：US20020050610A1

公开(公告)日：2002-05-02

申请号：US09921280

申请日：2001-08-02

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray

IPC: H01L029/788

CPC classification number: H01L29/42324 ,  H01L29/7886

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.

Abstract translation: 非易失性存储单元包括具有环形布置并包括浮动栅极的MOS晶体管，环形布置的中心处的中心电极并且围绕浮置栅极，以及沿环形布置的周边的至少一个外围电极。

公开(公告)号：US20020079545A1

公开(公告)日：2002-06-27

申请号：US09996071

申请日：2001-11-28

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray ,  Sigrid Thomas

IPC: H01L029/74

CPC classification number: H03K19/00315 ,  G11C5/145 ,  G11C8/08 ,  G11C16/0441 ,  G11C16/30

Abstract: A high voltage switching device includes a switching circuit for switching a high voltage to an output line and for providing a control signal. The high voltage switching device also includes a switching transistor connected to the switching circuit for switching a low voltage to the output line based upon the control signal. The output signal is controlled by a control circuit that sets up a control loop between the drop in the gate voltage level of the switching transistor and the voltage level of the output line that is controlled by the switching circuit.

Abstract translation: 高压开关装置包括用于将高电压切换到输出线并用于提供控制信号的开关电路。 高压开关装置还包括连接到开关电路的开关晶体管，用于基于控制信号将低电压切换到输出线。 输出信号由控制电路控制，该控制电路在开关晶体管的栅极电压电平的下降与由开关电路控制的输出线的电压电平之间建立控制回路。

公开(公告)号：US20020186599A1

公开(公告)日：2002-12-12

申请号：US10139621

申请日：2002-05-06

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Sigrid Thomas ,  Cyrille Dray

IPC: G11C007/00

CPC classification number: G11C16/0416

Abstract: A non-volatile memory architecture with a word-based organization includes one selection transistor per word. This selection transistor is used for the selection of the word by the source of the memory cells. In this way, the selection may be done directly by the output signals from the address decoders using low voltage. The switching of a high voltage to the gates and the drains of the memory cells is done independently of this selection. This enables the required number of high voltage switches to be reduced.

Abstract translation: 具有基于单词的组织的非易失性存储器架构包括每个字的一个选择晶体管。 该选择晶体管用于由存储器单元的源选择单词。 以这种方式，可以通过使用低电压的地址解码器的输出信号直接进行选择。 独立于该选择，高电压切换到存储器单元的栅极和漏极。 这使得能够减少所需数量的高压开关。

公开(公告)号：US20030063498A1

公开(公告)日：2003-04-03

申请号：US10228164

申请日：2002-08-26

Applicant: STMICROELECTRONICS S.A.

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C007/00

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

公开(公告)号：US20020175353A1

公开(公告)日：2002-11-28

申请号：US10126442

申请日：2002-04-19

Applicant: STMicroelectronics S.A.

Inventor： Cyrille Dray ,  Richard Fournel

IPC: H01L047/00 ,  H01L029/80

CPC classification number: G11C16/0433 ,  H01L27/115

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

Abstract translation: FAMOS存储器包括存储器单元，其中每个存储单元包括绝缘栅极晶体管，以及具有连接到绝缘栅极晶体管的源极的漏极的第一存取晶体管。 FAMOS存储器还包括绝缘晶体管，其具有分别连接到同一行的两个相邻单元的绝缘栅极晶体管的源极的漏极和源极。 每个绝缘栅极晶体管具有环形结构，并且梯形分离区域使得同一行的单元绝缘。

公开(公告)号：US20020176289A1

公开(公告)日：2002-11-28

申请号：US10117446

申请日：2002-04-03

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Cyrille Dray ,  Daniel Caspar

IPC: G11C007/00

CPC classification number: G11C16/0416 ,  G11C16/0408

Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

Abstract translation: FAMOS存储单元被电擦除。 可以通过向基板施加比施加到源极的电压的低至少4伏的电压和施加到漏极的电压来电存储FAMOS存储单元。 施加到基板的电压也小于预定的限制，高于该预定限度，存储单元被破坏。