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公开(公告)号：US20220308892A1
公开(公告)日：2022-09-29
申请号：US17654537
申请日：2022-03-11
IPC分类号： G06F9/4401 , G06F9/30
摘要： In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
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公开(公告)号：US11915008B2
公开(公告)日：2024-02-27
申请号：US17654537
申请日：2022-03-11
IPC分类号： G06F9/44 , G06F9/4401 , G06F9/30
CPC分类号： G06F9/4403 , G06F9/30101
摘要： In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
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3.发明申请公开(公告)号：US20210055881A1
公开(公告)日：2021-02-25
申请号：US17087070
申请日：2020-11-02
IPC分类号： G06F3/06
摘要： A method for operating a differential memory includes: operating a main memory module differentially while executing a first program; copying first logic data from a first submodule of the main memory module to an auxiliary memory module; storing third logic data associated with a second program in a second submodule of the main memory module by overwriting second logic data associated with the first program, while maintaining the first logic data contained in the first submodule of the main memory module unaltered, where the second logic data are complementary to the first logic data; when a request for reading the first logic data is received during the storing of the third logic data in the second submodule of the main memory module, reading the first logic data from the auxiliary memory module; and executing the first or second programs by operating the main memory module in single-ended mode.
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公开(公告)号：US20220230682A1
公开(公告)日：2022-07-21
申请号：US17657861
申请日：2022-04-04
摘要： A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
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5.发明申请公开(公告)号：US20190213000A1
公开(公告)日：2019-07-11
申请号：US16225557
申请日：2018-12-19
摘要： A method for management of a differential memory includes storing first logic data associated with a first informative content in an auxiliary memory module of the differential memory; storing third logic data associated with a second informative content in a second submodule of a main memory module by overwriting second logic data associated with the first informative content while maintaining the first logic data contained in a first submodule of the main memory module unaltered; when the third logic data is being stored, reading the first logic data from the auxiliary memory module in a single-ended mode in response to a request for reading the first informative content; otherwise, reading the first logic data from the first submodule; and reading the third logic data in single-ended mode.
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