-
公开(公告)号：US20220308892A1
公开(公告)日：2022-09-29
申请号：US17654537
申请日：2022-03-11
IPC: G06F9/4401 , G06F9/30
Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
-
公开(公告)号：US20180329774A1
公开(公告)日：2018-11-15
申请号：US15975507
申请日：2018-05-09
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
-
公开(公告)号：US20210357538A1
公开(公告)日：2021-11-18
申请号：US17443497
申请日：2021-07-27
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Giovanni Disirio
IPC: G06F21/83 , G06F21/64 , G06F12/02 , G06F9/38 , G06F9/445 , H04L9/32 , G06F21/57 , G09C1/00 , G06F21/74 , H04W12/106
Abstract: A hardware secure element includes a processing unit and a receiver circuit configured to receive data comprising a command field and a parameter field adapted to contain a plurality of parameters. The hardware secure element also includes at least one hardware parameter check module configured to receive at an input a parameter to be processed selected from the plurality of parameters, and to process the parameter to be processed to verify whether the parameter has given characteristics. The hardware parameter check module has associated one or more look-up tables configured to receive at an input the command field and a parameter index identifying the parameter to be processed by the hardware parameter check module, and to determine for the command field and the parameter index a configuration data element.
-
公开(公告)号：US10754723B2
公开(公告)日：2020-08-25
申请号：US15975507
申请日：2018-05-09
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Roberta Vittimani
Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
-
5.发明授权公开(公告)号：US12117949B2
公开(公告)日：2024-10-15
申请号：US18364786
申请日：2023-08-03
Applicant: STMicroelectronics Application GMBH
Inventor： Rolf Nandlinger , Roberto Colombo
CPC classification number: G06F13/28 , G06F9/30105 , G06F9/3877 , G06F13/4282 , G06F21/602 , G06F21/72
Abstract: In an embodiment, a processing system comprises a microprocessor programmable via software instructions, a memory controller configured to be coupled to a memory, a communication system coupling the microprocessors to the memory controller, a cryptographic co-processor and a first communication interface. The processing system also comprises first and second configurable DMA channels. In a first configuration, the first DMA channel is configured to transfer data from the memory to the cryptographic co-processor, and the second DMA channel is configured to transfer the encrypted data via two loops from the cryptographic co-processor to the first communication interface. In a second configuration, the second DMA channel is configured to transfer received data via two loops from the first communication interface to the cryptographic co-processor, and the first DMA channel is configured to transfer the decrypted data from the cryptographic co-processor to the memory.
-
Patent Agency Ranking
公开(公告)号：US11915008B2
公开(公告)日：2024-02-27
申请号：US17654537
申请日：2022-03-11
IPC: G06F9/44 , G06F9/4401 , G06F9/30
CPC classification number: G06F9/4403 , G06F9/30101
Abstract: In an embodiment, a hardware configuration circuit reads and decodes an encoded life-cycle data and provides the decoded life-cycle data to a hardware circuit. A reset circuit monitors an external reset signal received via a reset terminal and, in response to determining that the external reset signal has a first logic level, executes a reset, a configuration, and a wait phase. The reset circuit waits until the external reset signal has a second logic level. A communication interface is activated during the wait phase and configured to receive a request. A hardware verification circuit generates a life-cycle advancement request signal when the request includes a given reference password and a reset circuit is in the wait phase. A write circuit writes a bit of the encoded life-cycle data stored in a non-volatile memory when the life-cycle advancement request signal is set, advancing the life-cycle to a given predetermined life-cycle stage.
-
公开(公告)号：US11822934B2
公开(公告)日：2023-11-21
申请号：US17341054
申请日：2021-06-07
Inventor： Roberto Colombo , Om Ranjan
CPC classification number: G06F9/44505 , G06F11/1004 , G06F13/36 , H04L9/0643 , H04L9/3247
Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.
-
公开(公告)号：US11764807B2
公开(公告)日：2023-09-19
申请号：US17858782
申请日：2022-07-06
Inventor： Vivek Mohan Sharma , Roberto Colombo
CPC classification number: H03M13/1105 , H03M13/611
Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.
-
公开(公告)号：US20220334865A1
公开(公告)日：2022-10-20
申请号：US17657856
申请日：2022-04-04
Inventor： Roberto Colombo , Vivek Mohan Sharma
Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.
-
10.发明授权公开(公告)号：US11321492B2
公开(公告)日：2022-05-03
申请号：US17107183
申请日：2020-11-30
Inventor： Roberto Colombo , Nicolas Bernard Grossier , Giovanni Disirio , Lorenzo Re Fiorentin
IPC: G06F9/448 , G06F12/02 , G06F9/38 , G06F9/30 , G06F21/71 , G06F21/60 , H04L9/06 , G06F11/07 , G06F21/57 , G06F21/72 , G06F21/77 , H03K19/17728
Abstract: A hardware secure element is described. The hardware secure element includes a microprocessor and a memory, such as a non-volatile memory. The memory stores a plurality of software routines executable by the microprocessor. Each software routine starts at a respective memory start address. The hardware secure element also includes a receiver circuit and a hardware message handler module. The receiver circuit is configured to receive command data that includes a command. The hardware message handler module is configured to determine a software routine to be executed by the microprocessor as a function of the command, and also configured to provide address data to the microprocessor that indicates the software routine to be executed.
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.025 seconds)
