DECODING ARCHITECTURE AND METHOD FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES
    1.
    发明申请
    DECODING ARCHITECTURE AND METHOD FOR PHASE CHANGE NON-VOLATILE MEMORY DEVICES 有权
    解码结构和相位改变非易失性存储器件的方法

    公开(公告)号:US20130258766A1

    公开(公告)日:2013-10-03

    申请号:US13780280

    申请日:2013-02-28

    Abstract: A decoding system for a phase change non-volatile memory device having a memory array may include a column decoder that selects at least one column of the memory array during programming operations. The decoding system includes a selection circuit that includes selection switches on a number of hierarchical decoding levels for defining a conductive path between at least one column and a driving stage. A biasing circuit may supply biasing signals to the selection switches for defining the first conductive path and bringing the selected column to a programming voltage value. The programming selection circuit may have protection elements between columns and the selection switches. The selection switches and the protection elements may include metal oxide semiconductor (MOS) transistors having an upper threshold voltage level lower than the programming voltage.

    Abstract translation: 具有存储器阵列的相变非易失性存储器件的解码系统可以包括在编程操作期间选择存储器阵列的至少一列的列解码器。 解码系统包括选择电路,其包括用于限定至少一个列和驱动级之间的导电路径的多个分层解码级别的选择开关。 偏置电路可以向选择开关提供偏置信号,用于限定第一导电路径并使所选列进入编程电压值。 编程选择电路可以具有列和选择开关之间的保护元件。 选择开关和保护元件可以包括具有比编程电压低的上阈值电压电平的金属氧化物半导体(MOS)晶体管。

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