公开(公告)号：US20160351264A1

公开(公告)日：2016-12-01

申请号：US14970732

申请日：2015-12-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Francesca GRANDE ,  Alfredo Signorello ,  SantiNunzioAntonino Pagano ,  Maria Giaquinta

IPC: G11C16/14 ,  G11C16/08

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/16

Abstract: A non-volatile memory device includes a memory array with memory cells arranged in rows and columns. Each cell has respective current-conduction regions and a control-gate region. The control-gate regions of the memory cells of a same row are coupled to a control-gate terminal and biased at a respective control-gate voltage. A control-gate decoder selects and biases the control-gate regions of the rows at respective control voltages according to operations to be performed on the memory cells. The current-conduction regions of the memory cells are arranged within a same bulk well, and the control-gate decoder has a number of driver blocks each of which supplies the control-gate voltages to a respective number of rows of the array. The driver blocks are provided in respective biasing wells, separate and distinct from one another.

Abstract translation: 非易失性存储器件包括具有以行和列排列的存储器单元的存储器阵列。 每个单元具有各自的导电区域和控制栅极区域。 同一行的存储单元的控制栅极区域耦合到控制栅极端子并且以相应的控制栅极电压偏置。 控制栅解码器根据对存储器单元执行的操作，在各个控制电压下选择并偏置行的控制栅极区域。 存储器单元的导通区域被布置在相同的体积阱中，并且控制栅极解码器具有多个驱动器块，每个驱动器块将控制栅极电压提供给阵列的相应数量的行。 驱动器块设置在各自的偏置井中，彼此分开且不同。

公开(公告)号：US20210319836A1

公开(公告)日：2021-10-14

申请号：US17224024

申请日：2021-04-06

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco LA ROSA ,  Enrico CASTALDO ,  Francesca GRANDE ,  Santi Nunzio Antonino PAGANO ,  Giuseppe NASTASI ,  Franco ITALIANO

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11529

Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

公开(公告)号：US20130258766A1

公开(公告)日：2013-10-03

申请号：US13780280

申请日：2013-02-28

Applicant: STMicroelectronics S.r.l.

Inventor： Antonino CONTE ,  Francesca GRANDE ,  Alberto Jose' DIMARTINO ,  Alfredo SIGNORELLO

IPC: G11C13/00

CPC classification number: G11C13/0009 ,  G11C5/146 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2207/005

Abstract: A decoding system for a phase change non-volatile memory device having a memory array may include a column decoder that selects at least one column of the memory array during programming operations. The decoding system includes a selection circuit that includes selection switches on a number of hierarchical decoding levels for defining a conductive path between at least one column and a driving stage. A biasing circuit may supply biasing signals to the selection switches for defining the first conductive path and bringing the selected column to a programming voltage value. The programming selection circuit may have protection elements between columns and the selection switches. The selection switches and the protection elements may include metal oxide semiconductor (MOS) transistors having an upper threshold voltage level lower than the programming voltage.

Abstract translation: 具有存储器阵列的相变非易失性存储器件的解码系统可以包括在编程操作期间选择存储器阵列的至少一列的列解码器。 解码系统包括选择电路，其包括用于限定至少一个列和驱动级之间的导电路径的多个分层解码级别的选择开关。 偏置电路可以向选择开关提供偏置信号，用于限定第一导电路径并使所选列进入编程电压值。 编程选择电路可以具有列和选择开关之间的保护元件。 选择开关和保护元件可以包括具有比编程电压低的上阈值电压电平的金属氧化物半导体（MOS）晶体管。