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    Voltage-regulator circuit, corresponding electronic device and method
    2.
    发明授权
    Voltage-regulator circuit, corresponding electronic device and method 有权

    公开(公告)号：US10126768B2

    公开(公告)日：2018-11-13

    申请号：US15392823

    申请日：2016-12-28

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Carmelo Burgio ,  Mauro Giacomini

    IPC: G05F1/575

    Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.

    Clock recovery method, corresponding circuit and system
    3.
    发明授权
    Clock recovery method, corresponding circuit and system 有权

    公开(公告)号：US11637683B2

    公开(公告)日：2023-04-25

    申请号：US17335336

    申请日：2021-06-01

    Applicant: STMicroelectronics S.r.l.

    Inventor： Carmelo Burgio ,  Walter Girardi ,  Sergio Lecce

    IPC: H04L1/00 ,  H04L7/04 ,  H04L7/00

    Abstract: An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

    VOLTAGE-REGULATOR CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD
    4.
    发明申请
    VOLTAGE-REGULATOR CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD 审中-公开

    公开(公告)号：US20170329360A1

    公开(公告)日：2017-11-16

    申请号：US15392823

    申请日：2016-12-28

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Carmelo Burgio ,  Mauro Giacomini

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/10 ,  G05F1/56 ,  H02M3/1584 ,  H02M3/33515 ,  H02M2001/0045

    Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.

    Dynamic range control method and device, apparatus and computer program product
    5.
    发明授权
    Dynamic range control method and device, apparatus and computer program product 有权
    动态范围控制方法及装置，装置及计算机程序产品

    公开(公告)号：US09559717B1

    公开(公告)日：2017-01-31

    申请号：US15053649

    申请日：2016-02-25

    Applicant: STMicroelectronics S.R.L.

    Inventor： Carmelo Burgio

    IPC: H03M1/66 ,  G06F3/16

    CPC classification number: H03M1/66 ,  G06F3/165 ,  H03G7/002 ,  H03G7/007 ,  H03M1/0863 ,  H03M1/1023 ,  H03M1/70 ,  H04R3/00 ,  H04R3/04 ,  H04R2430/01

    Abstract: In a signal processing chain producing an analog output signal from a digital input signal, dynamic range control applies to the analog output signal a dynamic range control gain as a function of an input gain applied to the digital input signal. The dynamic range control gain is applied to the analog output signal with a delay relative to the input gain applied to the digital input signal. A first flag signal is generated for the analog output signal and a second flag signal for the digital input signal, each flag assuming first and second levels and set to the first level when the signal from which the flag is generated is within a certain amplitude range. The first and second flag signals are compared and delay of application of the dynamic range control gain to the analog output signal controlled as a function of a result of the comparison.

    Abstract translation: 在产生来自数字输入信号的模拟输出信号的信号处理链中，动态范围控制适用于模拟输出信号作为施加到数字输入信号的输入增益的函数的动态范围控制增益。 相对于施加到数字输入信号的输入增益，动态范围控制增益被应用于模拟输出信号。 对于模拟输出信号产生第一标志信号和用于数字输入信号的第二标志信号，每个标志假设第一和第二电平并且当产生标志的信号在一定幅度范围内时被设置为第一电平 。 比较第一和第二标志信号，并将动态范围控制增益的应用延迟作为比较结果的函数而被控制的模拟输出信号。

    METHOD AND DEVICES FOR PROCESSING RADAR SIGNALS
    9.
    发明申请
    METHOD AND DEVICES FOR PROCESSING RADAR SIGNALS 有权
    用于处理雷达信号的方法和设备

    公开(公告)号：US20140327566A1

    公开(公告)日：2014-11-06

    申请号：US13888025

    申请日：2013-05-06

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Carmelo Burgio ,  Dario Catalano ,  Giampiero Borgonovo

    IPC: G01S13/72

    CPC classification number: G01S13/72 ,  G01S7/354 ,  G01S13/343 ,  G01S13/42 ,  G01S13/536 ,  G01S13/931 ,  G01S2013/0245 ,  G01S2013/9375

    Abstract: A method for processing signals received by a plurality of receiving antennas in a radar system, for example for road safety, which emits sequences of chirp-modulated signals, wherein the received signals are mixed with local replicas of the transmitted signals so as to generate, for each receiving antenna, a sequence of detection signals. The detection signals are subjected to Fourier-transform processing and beam-forming processing for generating values of range, azimuth, and speed for at least one obstacle or “target” detected by the radar system. The method includes an acquisition process for yielding approximate values of range and azimuth of the obstacle, and a tracking process for yielding accurate range, azimuth and speed values of the obstacle itself.

    Abstract translation: 一种用于处理由雷达系统中的多个接收天线接收的信号，例如用于道路安全的方法，其发射啁啾调制信号序列，其中所接收的信号与发送信号的本地副本混合， 对于每个接收天线，检测信号的序列。 检测信号进行傅里叶变换处理和波束成形处理，用于产生由雷达系统检测到的至少一个障碍物或“目标”的范围，方位角和速度值。 该方法包括用于产生障碍物的范围和方位角的近似值的获取过程，以及用于产生障碍物本身的精确范围，方位角和速度值的跟踪处理。

    Voltage-regulator circuit, corresponding electronic device and method
    10.
    发明授权
    Voltage-regulator circuit, corresponding electronic device and method 有权

    公开(公告)号：US10591939B2

    公开(公告)日：2020-03-17

    申请号：US16161983

    申请日：2018-10-16

    Applicant: STMicroelectronics S.r.l.

    Inventor： Carmelo Burgio ,  Mauro Giacomini

    IPC: G05F1/575 ,  G05F1/10 ,  G05F1/56 ,  H02M3/158 ,  H02M3/335 ,  H02M1/00

    Abstract: A voltage-regulator circuit with a current-adder output node for supplying a load with a load current at a regulated output voltage includes an analog portion sensitive to the output voltage and including one or more reference-voltage sources. The analog portion applies to the current-adder node a first current that is a function of the difference between the output voltage and the reference voltage. A digital portion including an integrator is sensitive to the first current. The integrator is coupled to a current source for applying to the current-adder node a second current so that the first current and the second current supply on the current-adder output a load current at the aforesaid regulated output voltage.

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