公开(公告)号：US10763192B2

公开(公告)日：2020-09-01

申请号：US16212581

申请日：2018-12-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Dario Vitello

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

Abstract: A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.

公开(公告)号：US12211763B2

公开(公告)日：2025-01-28

申请号：US17549058

申请日：2021-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Derai ,  Dario Vitello

IPC: H01L23/29 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495

Abstract: A method of manufacturing semiconductor devices, such as QFN/BGA flip-chip type packages, arranging on a leadframe one or more semiconductor chips or dice having a first side facing towards the leadframe and electrically coupled therewith and a second side facing away from the leadframe. The method also includes molding an encapsulation on the semiconductor chip(s) arranged on the leadframe, where the encapsulation has an outer surface opposite the leadframe and comprises laser direct structuring (LDS) material. Laser direct structuring processing is applied to the LDS material of the encapsulation to provide metal vias between the outer surface of the encapsulation and the second side of the semiconductor chip(s) and as well as a metal pad at the outer surface of the encapsulation.

公开(公告)号：US11721614B2

公开(公告)日：2023-08-08

申请号：US17124094

申请日：2020-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Michele Derai ,  Dario Vitello

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/49537 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49579 ,  H01L23/49827

Abstract: A System in Package, SiP semiconductor device includes a substrate of laser direct structuring, LDS, material. First and second semiconductor die are arranged at a first and a second leadframe structure at opposite surfaces of the substrate of LDS material. Package LDS material is molded onto the second surface of the substrate of LDS material. The first semiconductor die and the package LDS material lie on opposite sides of the substrate of LDS material. A set of electrical contact formations are at a surface of the package molding material opposite the substrate of LDS material. The leadframe structures include laser beam processed LDS material. The substrate of LDS material and the package LDS material include laser beam processed LDS material forming at least one electrically-conductive via providing at least a portion of an electrically-conductive line between the first semiconductor die and an electrical contact formation at the surface of the package molding material opposite the substrate.

公开(公告)号：US09922947B2

公开(公告)日：2018-03-20

申请号：US15141621

申请日：2016-04-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Dario Vitello ,  Federico Frego ,  Salvatore Latino

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05011 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05097 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/48463 ,  H01L2924/3512

Abstract: Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes a continuous metal layer, a first discontinuous metal layer, a second discontinuous metal layer, and dielectric material. The first discontinuous metal layer and the second discontinuous metal layer each include a plurality of holes that are arranged in a pattern. The plurality of holes of the first discontinuous metal layer overlaps at least two of the plurality of holes of the second discontinuous metal layer. The dielectric material is formed between the metal layers and fills the plurality of holes of the first and second discontinuous metal layers.

公开(公告)号：US20170317039A1

公开(公告)日：2017-11-02

申请号：US15141621

申请日：2016-04-28

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Dario Vitello ,  Federico Frego ,  Salvatore Latino

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05011 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05097 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/48463 ,  H01L2924/3512

Abstract: Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes a continuous metal layer, a first discontinuous metal layer, a second discontinuous metal layer, and dielectric material. The first discontinuous metal layer and the second discontinuous metal layer each include a plurality of holes that are arranged in a pattern. The plurality of holes of the first discontinuous metal layer overlaps at least two of the plurality of holes of the second discontinuous metal layer. The dielectric material is formed between the metal layers and fills the plurality of holes of the first and second discontinuous metal layers.