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公开(公告)号：US09627066B1
公开(公告)日：2017-04-18
申请号：US15210709
申请日：2016-07-14
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Pasotti , Fabio de Santis , Roberto Bregoli , Dario Livornesi
CPC classification number: G11C16/0441 , G11C16/04 , G11C16/0408 , G11C16/10 , G11C16/14 , G11C16/26
Abstract: A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node. The second capacitor includes a third plate coupled to the second storage node and having an opposite fourth plate. The second plate is coupled to the fourth plate, and the first body of the access transistor is coupled to the second body and the third body.
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公开(公告)号：US20200161966A1
公开(公告)日：2020-05-21
申请号：US16677387
申请日：2019-11-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio de Santis , Dario Livornesi
Abstract: A charge pump circuit has a plurality of charge pump stages cascaded to one another between an input terminal and an output terminal to provide an output voltage having a boosted value with respect to the input voltage. A clock generator is configured to generate a clock signal provided to the charge pump stages to perform the boosting of the input voltage. An output-voltage regulation feedback closed-loop is coupled to the clock generator to perform a regulation of the output voltage based on a feedback voltage. A discharge control stage is configured to control a discharge of the charge pump circuit by generating a first discharge control signal configured to disable the output-voltage regulation feedback closed-loop or a second discharge control signal configured to reduce the frequency of the clock signal.
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公开(公告)号：US10862392B2
公开(公告)日：2020-12-08
申请号：US16677387
申请日：2019-11-07
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio de Santis , Dario Livornesi
Abstract: A charge pump circuit has a plurality of charge pump stages cascaded to one another between an input terminal and an output terminal to provide an output voltage having a boosted value with respect to the input voltage. A clock generator is configured to generate a clock signal provided to the charge pump stages to perform the boosting of the input voltage. An output-voltage regulation feedback closed-loop is coupled to the clock generator to perform a regulation of the output voltage based on a feedback voltage. A discharge control stage is configured to control a discharge of the charge pump circuit by generating a first discharge control signal configured to disable the output-voltage regulation feedback closed-loop or a second discharge control signal configured to reduce the frequency of the clock signal.
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