中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.014 seconds)

    Non volatile memory cell and memory array
    3.
    发明授权
    Non volatile memory cell and memory array 有权

    公开(公告)号：US09627066B1

    公开(公告)日：2017-04-18

    申请号：US15210709

    申请日：2016-07-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： Marco Pasotti ,  Fabio de Santis ,  Roberto Bregoli ,  Dario Livornesi

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/14

    CPC classification number: G11C16/0441 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: A non-volatile memory cell for storing a single bit is disclosed. The non-volatile memory cell includes an access transistor including a gate, a first body, a first source/drain node, and a second source/drain node. The non-volatile memory cell also includes a first floating gate storage transistor that has a third source/drain node, a second body, a fourth source/drain node, and a first floating gate including a first storage node. The third source/drain node is coupled to the second source/drain node. The non-volatile memory cell further includes a first capacitor, a second capacitor, and a second floating gate storage transistor. The first capacitor has a first plate coupled to the first storage node and an opposite second plate. The second floating gate storage transistor includes a fifth source/drain node, a third body, a sixth source/drain node, a second floating gate including a second storage node. The fifth source/drain node is coupled to the fourth source/drain node. The second capacitor includes a third plate coupled to the second storage node and having an opposite fourth plate. The second plate is coupled to the fourth plate, and the first body of the access transistor is coupled to the second body and the third body.

    Non-volatile memory cell with single poly, floating gate extending over two wells
    4.
    发明授权
    Non-volatile memory cell with single poly, floating gate extending over two wells 有权

    公开(公告)号：US12148473B2

    公开(公告)日：2024-11-19

    申请号：US17697846

    申请日：2022-03-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Roberto Bregoli ,  Vikas Rana

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H10B41/35 ,  H10B41/70

    Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.

    NON-VOLATILE MEMORY CELL
    5.
    发明公开
    NON-VOLATILE MEMORY CELL 审中-公开

    公开(公告)号：US20230328979A1

    公开(公告)日：2023-10-12

    申请号：US18185575

    申请日：2023-03-17

    Applicant: STMicroelectronics S.r.l.

    Inventor： Roberto Bregoli ,  Alessandro Ferretti ,  Federica Rosa

    IPC: H10B41/70 ,  G11C16/04 ,  G11C16/10 ,  H10B41/35 ,  G11C16/14

    CPC classification number: H10B41/70 ,  G11C16/045 ,  G11C16/10 ,  G11C16/14 ,  H10B41/35

    Abstract: A non-volatile memory cell includes a first well of a first conductivity type and a second well of a second conductivity type in a body adjacent to each other; a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type; a control gate region, of the first or second conductivity type, in the second well; a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor; and a floating gate region. The floating gate region has a programming portion overlying the first well and a capacitive portion overlying the second well. The floating gate region forms, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element.

    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF
    6.
    发明申请
    SINGLE POLY, FLOATING GATE, FEW TIME PROGRAMMABLE NON-VOLATILE MEMORY DEVICE AND BIASING METHOD THEREOF 有权

    公开(公告)号：US20220319598A1

    公开(公告)日：2022-10-06

    申请号：US17697846

    申请日：2022-03-17

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

    Inventor： Roberto Bregoli ,  Vikas Rana

    IPC: G11C16/04 ,  H01L27/11524 ,  H01L27/1156 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.

Patent Agency Ranking