公开(公告)号：US20230328979A1

公开(公告)日：2023-10-12

申请号：US18185575

申请日：2023-03-17

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto Bregoli ,  Alessandro Ferretti ,  Federica Rosa

IPC: H10B41/70 ,  G11C16/04 ,  G11C16/10 ,  H10B41/35 ,  G11C16/14

CPC classification number: H10B41/70 ,  G11C16/045 ,  G11C16/10 ,  G11C16/14 ,  H10B41/35

Abstract: A non-volatile memory cell includes a first well of a first conductivity type and a second well of a second conductivity type in a body adjacent to each other; a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type; a control gate region, of the first or second conductivity type, in the second well; a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor; and a floating gate region. The floating gate region has a programming portion overlying the first well and a capacitive portion overlying the second well. The floating gate region forms, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element.